IP Library Granted Patent US 9,401,403
Granted Patent B2
US 9,401,403 · App. 14/636,163 · Granted Jul 26, 2016

Nitride semiconductor structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,401,403
App. No.
14/636,163
Granted
Jul 26, 2016
Kind
B2
Abstract

A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more.

Claims (30)

1. A nitride semiconductor structure comprising:

a semiconductor substrate, and

a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers,

wherein the semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order,

the surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more, and

a central portion of the semiconductor substrate has an oxygen concentration higher than that of an end portion of the semiconductor substrate.

2. The nitride semiconductor structure according to claim 1 , wherein the semiconductor substrate has an oxygen concentration ranging from 1×10 17 cm −3 to 5×10 18 cm −3 both inclusive.

3. A nitride semiconductor structure comprising:

a semiconductor substrate, and

a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers,

wherein the semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order,

the surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more, and

the semiconductor substrate has an oxygen concentration distribution, and a thickness of the layer comprising the plural nitride semiconductor layers above a high-oxygen concentration region of the semiconductor substrate is larger than a thickness of the layer comprising the plural nitride semiconductor layers above a low-oxygen concentration region of the semiconductor substrate.

4. A nitride semiconductor structure comprising:

a semiconductor substrate, and

a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers,

wherein the semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order,

the surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more, and

the surface region has a lower oxygen concentration than the internal region.

5. The nitride semiconductor structure according to claim 1 , wherein the layer comprising the plural nitride semiconductor layers has a thickness of 1000 nm or more.

6. The nitride semiconductor structure according to claim 1 , wherein a source electrode, a drain electrode, and a gate electrode are formed on the layer comprising the plural nitride semiconductor layers.

7. The nitride semiconductor structure according to claim 6 , wherein a semiconductor layer containing a p-type impurity is formed between the gate electrode and the layer comprising the plural nitride semiconductor layers.

8. The nitride semiconductor structure according to claim 6 , wherein the semiconductor substrate is electrically connected to the source electrode or the drain electrode.

9. The nitride semiconductor structure according to claim 1 , wherein a positive electrode and a negative electrode are formed on the layer comprising the plural nitride semiconductor layers.

10. The nitride semiconductor structure according to claim 9 , wherein the semiconductor substrate is electrically connected to the positive electrode or the negative electrode.

11. The nitride semiconductor structure according to claim 1 , wherein the layer comprising the plural nitride semiconductor layers comprises a buffer layer, a channel layer formed over the buffer layer, and a barrier layer formed over the channel layer and having a larger bandgap energy than the channel layer.

12. The nitride semiconductor structure according to claim 11 , wherein the buffer layer comprises carbon.

13. The nitride semiconductor structure according to claim 12 , wherein the carbon comprised in the buffer layer has a concentration ranging from 1×10 18 cm −3 to 1×10 20 cm −3 both inclusive.

14. The nitride semiconductor structure according to claim 11 , wherein the channel layer comprises carbon.

15. The nitride semiconductor structure according to claim 14 , wherein the carbon comprised in the channel layer has a concentration of 1×10 18 cm −3 or less.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069503/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2015
From: UMEDA, HIDEKAZU; ISHIDA, MASAHIRO; UEDA, TETSUZO; UEDA, DAISUKE
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 035196/0658 →