IP Library Patent Application 14660915
Patent Application
App. No. 14/660,915

BANDGAP CIRCUIT

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Quick Facts
Patent No.
US None
App. No.
14/660,915
Filed
Mar 17, 2015
Examiner
TRAN, NGUYEN
Art Unit
2838
USPC
323/313
Abstract

A bandgap circuit has a pair of NPN bipolar devices that are connected to (i) generate a base-to-emitter voltage difference that is applied across an output-stage resistor and (ii) function as input devices for an amplifier stage that ensures that sufficient current is driven across the output-stage resistor to maintain a desired voltage difference. The desired voltage difference, which has a positive temperature coefficient, is combined with a base-to-emitter voltage of another NPN bipolar device having a negative temperature coefficient to provide a bandgap voltage that is substantially impervious to variations in operating temperature, voltage, and process corners. By using the same two bipolar devices to provide two different functions, there is no need for a separate CMOS-based opamp, which reduces the sources of process mismatch that can adversely affect the bandgap voltage compared to conventional bandgap circuits having bipolar devices and a separate CMOS-based opamp.

Claims (28)

1 . A bandgap circuit for generating a bandgap voltage based on a first voltage having a negative temperature coefficient and a second voltage having a positive temperature coefficient, the bandgap circuit comprising:

first circuitry that generates the first voltage; and

second circuitry that generates the second voltage, wherein the second circuitry comprises:

a first resistor having two terminals; and

first and second transistors that are connected to generate and apply the second voltage across the two terminals of the first resistor, wherein the first and second transistors are input devices of an amplifier in the bandgap circuit that causes current to be driven through the first resistor to maintain the two terminals of the first resistor at two different voltage levels corresponding to the second voltage.

2 . The bandgap circuit of claim 1 , wherein:

the first and second transistors are configured such that mirrored currents flow through the first and second transistors;

the first and second transistors are bipolar devices having their emitters shorted together and their bases respectively connected to the two terminals of the first resistor; and

the first and second transistors are sized such that the mirrored currents result in the first and second transistors having different current densities and different base-to-emitter voltages, such that the second voltage across the two terminals of the first resistor results from the bases of the first and second transistors having different voltages due to the emitters of the first and second transistors being shorted together.

3 . The bandgap circuit of claim 2 , wherein the first and second transistors are NPN bipolar devices.

4 . The bandgap circuit of claim 3 , wherein the first circuitry comprises a NPN bipolar device connected in series with the first resistor.

5 . The bandgap circuit of claim 4 , wherein the first resistor is connected in series between second and third resistors.

6 . The bandgap circuit of claim 1 , wherein the amplifier comprises:

the first and second transistors functioning as the input devices to the amplifier; and

a load comprising first and second current-mirror transistors connected to generate mirrored currents through the first and second transistors.

7 . The bandgap circuit of claim 6 , wherein:

the load further comprises first and second cascode transistors connected to increase output resistance of the load; and

the bandgap circuit further comprises a cascode generation stage connected to generate a bias voltage applied to the gates of the first and second cascode transistors.

8 . The bandgap circuit of claim 1 , further comprising:

a gain stage connected to receive an amplifier output signal from the amplifier and generate a gain-stage output signal; and

an output stage comprising, and connected in series, the first circuitry, the first resistor, and an output-stage device,

wherein the gain-stage output signal is applied to the gate of the output-stage device to generate the current flowing through the first resistor to drive the two terminals of the first resistor to maintain the two different voltage levels corresponding to the second voltage.

9 . The bandgap circuit of claim 8 , wherein the output stage further comprises one or more additional series-connected resistances.

10 . The bandgap circuit of claim 8 , further comprising stabilization circuitry connected between the amplifier and the gain stage to inhibit oscillations within the bandgap circuit.

11 . The bandgap circuit of claim 1 , further comprising a bias stage connected to provide bias current for one or more other stages in the bandgap circuit such that the bandgap circuit is self-biased.

12 . The bandgap circuit of claim 1 , further comprising a resistance-chain stage connected between the bandgap voltage and ground to provide one or more voltage levels between the bandgap voltage and ground.

13 . The bandgap circuit of claim 12 , wherein the resistance-chain stage comprises a series of resistors connected between the bandgap voltage and ground.

14 . The bandgap circuit of claim 12 , wherein the resistance-chain stage comprises a series of diode-connected transistors connected between the bandgap voltage and ground.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0359 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0341 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0974 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0095 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0112 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2015
From: WADHWA, SANJAY KUMAR
To: FREESCALE SEMICONDUCTOR, INC
Reel/Frame 035186/0480 →