IP Library Granted Patent US 9,666,664
Granted Patent B2
US 9,666,664 · App. 14/663,140 · Granted May 30, 2017

Semiconductor device

Inventors: Ryo Kajitani (Osaka, JP); Tetsuzo Ueda (Osaka, JP); Yoshiharu Anda (Osaka, JP); Naohiro Tsurumi (Kyoto, JP); Satoshi Nakazawa (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L29/0611H01L29/2003H01L29/205H01L29/402H01L29/404H01L29/51H01L29/66462H01L29/7786H01L29/78
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Quick Facts
Patent No.
US 9,666,664
App. No.
14/663,140
Granted
May 30, 2017
Kind
B2
Abstract

An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.

Claims (32)

1. A semiconductor device comprising:

a substrate;

a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor;

a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor;

a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer;

a first field plate electrode disposed on the second semiconductor layer; and

a second field plate electrode disposed on the first field plate electrode, wherein

the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode, and

in a view illustrating planar arrangement of the gate electrode, the source electrode, the first electrode, the second electrode and the drain electrode,

an element region includes the gate electrode, the source electrode, the first field plate electrode, the second field plate electrode and the drain electrode, and

the second field plate electrode is electrically connected to the source electrode through an outside region of the element region.

2. The semiconductor device according to claim 1 , wherein the gate electrode is disposed so as to partially cover the first field plate electrode.

3. The semiconductor device according to claim 1 , wherein the second field plate electrode has a thickness larger than a thickness of the gate electrode.

4. The semiconductor device according to claim 1 , wherein the second field plate electrode has a surface position higher than a surface position of the gate electrode.

5. The semiconductor device according to claim 1 , wherein the second field plate electrode is disposed so as not to cover a part of the gate electrode.

6. The semiconductor device according to claim 1 , wherein the gate electrode is disposed so as to fill a recessed portion formed in an upper surface of the second semiconductor layer.

7. The semiconductor device according to claim 1 , wherein a protective film is formed on the second semiconductor layer, and the gate electrode is formed on the protective film.

8. The semiconductor device according to claim 7 , wherein

the protective film has a recessed portion to expose the second semiconductor layer, and

the gate electrode is disposed so as to fill the recessed portion.

9. The semiconductor device according to claim 1 , wherein a protective film is interposed between the first field plate electrode and the second field plate electrode.

10. The semiconductor device according to claim 9 , wherein the first field plate electrode is directly connected to the second field plate electrode through an opening formed in the protective film.

11. The semiconductor device according to claim 9 , wherein the protective film comprises a first protective film and a second protective film, the first protective film is partially disposed under the gate electrode, and the first protective film has a thickness smaller than a thickness of the second protective film.

12. The semiconductor device according to claim 7 , wherein the protective film is made of one of SiN, SiO 2 , Al 2 O 3 , and AlN.

13. The semiconductor device according to claim 1 , wherein the first field plate electrode and the second field plate electrode are electrically connected to the source electrode.

14. The semiconductor device according to claim 1 , wherein the first semiconductor layer contains GaN, and the second semiconductor layer contains Al x Ga 1-x N (0≦x≦1).

15. The semiconductor device according to claim 1 , wherein the second semiconductor layer has a second recessed portion and a third recessed portion, and

the drain electrode is disposed so as to fill the second recessed portion and the source electrode is disposed so as to fill the third recessed portion.

16. The semiconductor device according to claim 1 , wherein in the view illustrating planar arrangement of the gate electrode, the source electrode, the first electrode, the second electrode and the drain electrode, the second field plate electrode overlaps the first field plate electrode, and does not overlap the gate electrode.

17. The semiconductor device according to claim 1 , wherein

in the view illustrating planar arrangement, the second field plate electrode includes a first portion extending in a first direction parallel to the source electrode and a second portion in the outside region extending in a second direction orthogonal to the first direction, and

the second portion of the second field plate electrode is disposed immediately above a part of the first field plate electrode.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069503/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2015
From: KAJITANI, RYO; UEDA, TETSUZO; ANDA, YOSHIHARU; TSURUMI, NAOHIRO; NAKAZAWA, SATOSHI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 035391/0866 →
Priority Claims (1)
JP 2012-217917 · Sep 28, 2012 · national
Continuity (2)
Continuation PCTJP2013005576 · Sep 20, 2013
Related Publication 20150194483A1 · Jul 9, 2015