IP Library Patent Application 14667229
Patent Application
App. No. 14/667,229

COMPUTER SYSTEMS AND METHODS FOR CONTEXT SWITCHING

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Quick Facts
Patent No.
US None
App. No.
14/667,229
Filed
Mar 24, 2015
Art Unit
2183
USPC
712/228
Abstract

A data processing system includes a plurality of contexts, a current context indicator configured to indicate a context of the plurality of contexts as the current context, an instruction queue configured to store fetched instructions for execution using in the current context, and a scheduler coupled to the context selector. The scheduler is configured to, in response to a context switch event, save a current context instruction state from the instruction queue to the corresponding instruction buffer of the current context, select a next context of the plurality of contexts, restore a context instruction state from the corresponding instruction buffer of the next context to the instruction queue, and set the current context indicator to indicate the selected next context as the current context.

Claims (36)

1 . A data processing system comprising:

a plurality of contexts, wherein each context includes a corresponding register file and a corresponding instruction buffer;

a current context indicator configured to indicate a context of the plurality of contexts as the current context;

an instruction queue configured to store fetched instructions for execution using the current context;

a scheduler coupled to the context selector and configured to, in response to a context switch event, save a current context instruction state from the instruction queue to the corresponding instruction buffer of the current context, select a next context of the plurality of contexts, restore a context instruction state from the corresponding instruction buffer of the next context to the instruction queue, and set the current context indicator to indicate the selected next context as the current context.

2 . The data processing system of claim 1 , wherein the current context instruction state comprises the fetched instructions of the current context.

3 . The data processing system of claim 1 , further comprising an instruction pipeline, wherein the instruction pipeline comprises the instruction queue, and a sequencer coupled to the instruction pipeline and configured to, in response to the context switch event, flush the pipeline.

4 . The data processing system of claim 3 , wherein the instruction pipeline is configured to, after the selected next context is set as the current context in response to the context switch event, continue instruction execution with the restored fetched instructions in the instruction queue.

5 . The data processing system of claim 4 , wherein the instruction pipeline comprises an instruction decode unit and is configured to continue execution with the restored fetched instructions by providing a next instruction of the restored fetched instructions to the instruction decode unit.

6 . The data processing system of claim 1 , wherein the context switch event comprises a cache miss.

7 . The data processing system of claim 1 , wherein the context switch event comprises a response to an interrupt.

8 . The data processing system of claim 1 , wherein each context of the plurality of contexts further comprises context scheduling information.

9 . The data processing system of claim 8 , wherein the context scheduling information in each context of the plurality of contexts includes a ready indicator, wherein the scheduler is configured to, in response to the context switch event, use the context scheduling information in each of the plurality of contexts to select a ready context as the next context.

10 . A data processing system comprising:

an instruction pipeline having an instruction queue configured to store fetched instructions, an instruction decode unit coupled to receive fetched instructions from the instruction queue, and an execution unit coupled to receive decoded instructions from the instruction decode unit;

a plurality of contexts coupled to the instruction pipeline, wherein each context includes a corresponding register file and a corresponding instruction buffer;

a current context indicator configured to indicate a context of the plurality of contexts as the current context;

a scheduler coupled to the context selector and configured to, in response to a context switch event, save the fetched instructions from the instruction queue to the corresponding instruction buffer of the current context, select a next context of the plurality of contexts, restore fetched instructions from the corresponding instruction buffer of the next context to the instruction queue, and set the current context indicator to indicate the selected next context as the current context.

11 . The data processing system of claim 10 , wherein the context switch event comprises a cache miss.

12 . The data processing system of claim 10 , wherein the context switch event comprises a response to an interrupt.

13 . The data processing system of claim 10 , wherein the context switch event comprises a message unavailable event.

14 . The data processing system of claim 13 , wherein each context of the plurality of contexts further comprises context scheduling information, and wherein the scheduler is configured to, in response to the context switch event, use the context scheduling information in each of the plurality of contexts to select a next ready context as the next context.

15 . In a data processing system having an instruction pipeline and a plurality of contexts, each context having a corresponding register file and a corresponding instruction buffer, a method comprising:

executing a current context by the instruction pipeline;

determining occurrence of a context switch event; and

in response to the context switch event, the method further comprises:

saving a current context instruction state from the instruction pipeline to the corresponding instruction buffer of the current context;

selecting a next context of the plurality of contexts; and

restoring a context instruction state to the instruction pipeline from the corresponding instruction buffer of the next context.

16 . The method of claim 15 , wherein the executing in the current context comprises storing fetched instructions into an instruction queue of the instruction pipeline, wherein the saving the current context instruction state comprises storing the fetched instruction from the instruction queue to the corresponding instruction buffer of the current context.

17 . The method of claim 16 , wherein the restoring the context instruction state comprises restoring fetched instructions from the corresponding instruction buffer of the next context to the instruction queue.

18 . The method of claim 17 , wherein after the restoring the context instruction state to the pipeline, the method further comprises:

setting the selected next context as the current context; and

executing the restored fetched instructions by the instruction pipeline.

19 . The method of claim 15 , wherein the context switch event is determined in response to one of a cache miss, a response to an interrupt, or a message unavailable event.

20 . The method of claim 15 , wherein in response to the context switch event, the method further comprises flushing the pipeline.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0341 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0974 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0095 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0112 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 4, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035571/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2015
From: WILSON, PETER J.; KAHNE, BRIAN C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 035244/0651 →