IP Library Granted Patent US 9,466,709
Granted Patent B2
US 9,466,709 · App. 14/744,958 · Granted Oct 11, 2016

Silicon-carbide trench gate MOSFETs

Inventor: Andrei Konstantinov (Sollentuna, SE)
Assignee: Fairchild Semiconductor Corporation
H01L29/7813H01L29/1037H01L29/1095H01L29/167H01L29/1608H01L29/4236
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Quick Facts
Patent No.
US 9,466,709
App. No.
14/744,958
Granted
Oct 11, 2016
Kind
B2
Abstract

In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Claims (61)

1. An apparatus comprising:

a silicon-carbide (SiC) substrate of a first conductivity type;

a drift region of the first conductivity type disposed in the SiC substrate on a front side of the SiC substrate;

a drain region disposed on a back side of the SiC substrate;

a shielding body region of a second conductivity type disposed in the drift region;

a source region of the first conductivity type disposed in the shielding body region;

a gate trench disposed in the SiC substrate, the gate trench having a depth that is greater than a depth of the source region and less than a depth of the shielding body region;

a gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench, the gate dielectric on the sidewall of the gate trench defining a first interface with the shielding body region, the gate dielectric on the bottom surface of the gate trench defining a second interface with the shielding body region;

a gate electrode disposed on the gate dielectric; and

a lateral channel region of the first conductivity type, the lateral channel region being disposed in the shielding body region along the second interface.

2. The apparatus of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. The apparatus of claim 1 , wherein the lateral channel region includes a donor ion implant.

4. The apparatus of claim 1 , further comprising:

a sub-contact implant region of the second conductivity type disposed in the shielding body region, the sub-contact implant region being disposed adjacent to the source region, the source region being disposed between the sub-contact implant region and the gate trench; and

a contact layer disposed on at least a portion of the sub-contact implant region and disposed on at least a portion of the source region, the contact layer establishing a first ohmic contact with the sub-contact implant region and a second ohmic contact with the source region.

5. The apparatus of claim 4 , wherein the sub-contact region is includes an aluminum ion implant.

6. The apparatus of claim 1 , wherein:

a portion of the gate dielectric is disposed on a portion of an upper surface of the source region; and

a portion of the gate electrode is disposed on the portion of the gate dielectric disposed on the upper surface of the source region.

7. The apparatus of claim 1 , wherein the lateral channel region is further disposed along an interface between the bottom surface of the gate trench and the drift region.

8. The apparatus of claim 1 , further comprising a threshold control region of the second conductivity type disposed in the shielding body region, the threshold control region being disposed below the source region and having a depth that is less than the depth of the shielding body region, the gate dielectric on the sidewall of the gate trench further defining an interface with the threshold control region.

9. The apparatus of claim 8 , wherein a surface doping concentration of the threshold control region is greater than a surface doping concentration of the shielding body region.

10. The apparatus of claim 8 , wherein:

the sidewall of the gate trench defines an angle of greater than 90 degrees with the bottom surface of the gate trench;

the lateral channel region is further disposed, in the shielding body region, along at least a portion of the first interface; and

the lateral channel region terminates at the threshold control region.

11. The apparatus of claim 1 , wherein:

the sidewall of the gate trench defines an angle of greater than 90 degrees with the bottom surface of the gate trench; and

the lateral channel region is further disposed, in the shielding body region, along at least a portion of the first interface.

12. An apparatus comprising:

a silicon-carbide (SiC) substrate of a first conductivity type;

a drift region of the first conductivity type disposed in the SiC substrate on a front side of the SiC substrate;

a drain region disposed on a back side of the SiC substrate;

a shielding body region of a second conductivity type disposed in the drift region;

a source region of the first conductivity type disposed in the shielding body region;

a threshold control region of the second conductivity type disposed in the shielding body region, the threshold control region being disposed below the source region and having a depth that is less than a depth of the shielding body region;

a gate trench disposed in the SiC substrate, the gate trench having a depth that is greater than a depth of the threshold control region and less than a depth of the shielding body region;

a gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench, the gate dielectric on the sidewall of the trench defining an interface with the threshold control region and a first interface with the drift region, the gate dielectric on the bottom surface of the trench defining a second interface with the drift region;

a gate electrode disposed on the gate dielectric; and

a lateral channel region of the first conductivity type, the lateral channel region being disposed in the shielding body region along the second interface,

the sidewall of the gate trench being spaced a first distance from the shielding body region, the first distance being less than or equal to a second distance, the second distance being a lateral width from a vertical edge of the shielding body region to a vertical edge of a zero-bias depletion region of the apparatus.

13. The apparatus of claim 12 , wherein a surface doping concentration of the threshold control region is greater than a surface doping concentration of the shielding body region.

14. The apparatus of claim 12 , further comprising:

a sub-contact implant region of the second conductivity type disposed in the shielding body region, the sub-contact implant region being disposed adjacent to the source region, the source region being disposed between the sub-contact implant region and the gate trench; and

a contact layer disposed on at least a portion of the sub-contact implant region and disposed on at least a portion of the source region, the contact layer establishing a first ohmic contact with the sub-contact implant region and a second ohmic contact with the source region.

15. An apparatus comprising:

a silicon carbide (SiC) substrate of a first conductivity type;

a drift region of the first conductivity type disposed in the SiC substrate on a front side of the SiC substrate;

a drain region disposed on a back side of the SiC substrate;

a shielding body region of a second conductivity type disposed in the drift region;

a source region of the first conductivity type disposed in the shielding body region;

a gate trench disposed in the SiC substrate, the gate trench having a depth that is greater than a depth of the source region and less than a depth of the shielding body region;

a gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench, the gate dielectric on the sidewall of the gate trench defining a first interface with the shielding body region, the gate dielectric on the bottom surface of the gate trench defining a second interface with the shielding body region, the sidewall of the gate trench defining an angle of greater than 90 degrees with the bottom surface of the gate trench;

a gate electrode disposed on the gate dielectric; and

a lateral channel region of the first conductivity type, the lateral channel region being disposed in the shielding body region along the second interface.

16. The apparatus of claim 15 , further comprising a threshold control region of the second conductivity type disposed in the shielding body region, the threshold control region being disposed below the source region and having a depth that is less than the depth of the shielding body region, the gate dielectric on the sidewall of the gate trench further defining an interface with the threshold control region.

17. The apparatus of claim 16 , wherein:

the lateral channel region is further disposed, in the shielding body region, along at least a portion of the first interface; and

the lateral channel region terminates at the threshold control implant region.

18. The apparatus of claim 15 , wherein the lateral channel region is further disposed, in the shielding body region, along at least a portion of the first interface.

19. The apparatus of claim 3 , wherein the donor ion implant includes a nitrogen ion implant.

Assignments (9)
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2015
From: TRANSIC AB
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 035905/0250 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2015
From: KONSTANTINOV, ANDREI
To: TRANSIC AB
Reel/Frame 035874/0996 →
Continuity (2)
Provisional Application 62096943 · Dec 26, 2014
Related Publication 20160190308A1 · Jun 30, 2016