Buffer circuit for voltage controlled oscillator
View Patent ↗A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.
1. A buffer circuit for use in a voltage controlled oscillator, comprising:
a first inverter for receiving a first oscillating signal and generating an inverted version of the first oscillating signal; and
a level-shifter circuit, comprising:
a first transistor having a gate terminal connected to the first inverter for receiving the inverted version of the first oscillating signal, and a first terminal that receives a supply voltage;
a second transistor having a gate terminal for receiving a second oscillating signal and a first terminal connected to a second terminal of the first transistor; and
a third transistor having a gate terminal for receiving the second oscillating signal and connected to the gate terminal of the second transistor, a first terminal connected to ground, and a second terminal connected to a second terminal of the second transistor for generating a buffer output signal.
2. The buffer circuit of claim 1 , further comprising a second inverter connected to the level shifter circuit for receiving the buffer output signal and generating an output signal, wherein the output signal is a level-shifted version of the second oscillating signal.
3. The buffer circuit of claim 2 , further comprising a fourth transistor having a gate terminal connected to the second terminal of the first transistor, and first and second terminals connected to ground, wherein the fourth transistor functions as a capacitor to filter high frequency components of the inverted version of the first oscillating signal.
4. The buffer circuit of claim 2 , wherein the first inverter comprises:
a fifth transistor having a gate terminal for receiving the first oscillating signal and a first terminal for receiving a supply voltage; and
a sixth transistor having a gate terminal for receiving the first oscillating signal and connected to the gate terminal of the fifth transistor, a first terminal connected to ground, and a second terminal connected to a second terminal of the first transistor, wherein the inverted version of the first oscillating signal is generated at the node between the second terminals of the fifth and sixth transistors.
5. The buffer circuit of claim 4 , wherein the second inverter comprises:
a seventh transistor having a gate terminal connected to the second terminal of the second transistor for receiving the buffer output signal and a first terminal for receiving the supply voltage; and
an eighth transistor having a gate terminal connected to the second terminal of the second transistor and to the gate terminal of the seventh transistor, a first terminal connected to ground, and a second terminal connected to a second terminal of the seventh transistor, wherein the output signal is generated at the node connecting the second terminals of the seventh and eighth transistors.
6. A voltage-controlled oscillator for a phase locked loop, comprising:
a voltage-to-current converter that receives an input voltage and generates an output current therefrom;
a ring oscillator connected to the voltage-to-current converter, wherein the ring oscillator includes a plurality of series connected inverters with a last one of the inverters having an output connected to a first one of the inverters, wherein the inverters receive the output current and generate a corresponding plurality of oscillating signals having a predetermined phase difference therebetween;
a voltage controlled oscillator buffer circuit including a plurality of PLL buffer circuits connected to the ring oscillator for receiving the oscillating signals, wherein each buffer circuit receives one of the oscillating signals and a previous one of the oscillating signals and generates an output signal, and wherein each of the PLL buffer circuits comprises:
a first inverter for receiving a first oscillating signal and generating an inverted version of the first oscillating signal; and
a level-shifter circuit, comprising:
a first transistor having a gate terminal connected to the first inverter for receiving the inverted version of the first oscillating signal, and a first terminal that receives a supply voltage;
a second transistor having a gate terminal for receiving a second oscillating signal and a first terminal connected to a second terminal of the first transistor; and
a third transistor having a gate terminal for receiving the second oscillating signal and connected to the gate terminal of the second transistor, a first terminal connected to ground, and a second terminal connected to a second terminal of the second transistor for generating a buffer output signal.
7. The buffer circuit of claim 6 , further comprising a second inverter connected to the level shifter circuit for receiving the buffer output signal and generating an output signal, wherein the output signal is a level-shifted version of the second oscillating signal.
8. The buffer circuit of claim 7 , further comprising a fourth transistor having a gate terminal connected to the second terminal of the first transistor, and first and second terminals connected to ground, wherein the fourth transistor functions as a capacitor to filter high frequency components of the inverted version of the first oscillating signal.
9. The buffer circuit of claim 7 , wherein the first inverter comprises:
a fifth transistor having a gate terminal for receiving the first oscillating signal and a first terminal for receiving a supply voltage; and
a sixth transistor having a gate terminal for receiving the first oscillating signal and connected to the gate terminal of the fifth transistor, a first terminal connected to ground, and a second terminal connected to a second terminal of the first transistor, wherein the inverted version of the first oscillating signal is generated at the node between the second terminals of the fifth and sixth transistors.
10. The buffer circuit of claim 9 , wherein the second inverter comprises:
a seventh transistor having a gate terminal connected to the second terminal of the second transistor for receiving the buffer output signal and a first terminal for receiving the supply voltage; and
an eighth transistor having a gate terminal connected to the second terminal of the second transistor and to the gate terminal of the seventh transistor, a first terminal connected to ground, and a second terminal connected to a second terminal of the seventh transistor, wherein the output signal is generated at the node connecting the second terminals of the seventh and eighth transistors.