Single capacitor, controlled output, inverter based positive/negative charge pump
View Patent ↗A charge pump includes first through fifth transistors and a capacitor. The first through fourth transistors are connected in cascade and form a control circuit. The second transistor has a gate connected to its drain and hence, acts as a diode. The charge pump receives a clock signal and a supply voltage and generates an output voltage where the level of the output voltage is controlled by varying a size of the second transistor.
1. A charge pump, comprising:
a control circuit for receiving a clock signal and an inverted version of the clock signal and generating a control signal and a first intermediate signal, wherein the control circuit comprises:
a first transistor having a first terminal for receiving a supply voltage and a gate terminal for receiving the first intermediate signal;
a second transistor having a gate terminal connected to a first terminal thereof and a second terminal connected to the second terminal of the first transistor for generating the control signal;
a third transistor having a gate terminal for receiving the clock signal and a first terminal connected to the first terminal of the second transistor; and
a fourth transistor having a gate terminal for receiving the inverted version of the clock signal, a first terminal connected to ground, and a second terminal connected to a second terminal of the third transistor for generating the first intermediate signal;
a fifth transistor having a gate terminal connected to the control circuit for receiving the control signal, a first terminal connected to the control circuit for receiving the first intermediate signal, and a second terminal for generating a second intermediate signal; and
a capacitor having a first terminal connected to the second terminal of the fifth transistor for receiving the second intermediate signal and a second terminal for receiving a delayed version of the clock signal, wherein the capacitor generates an output voltage at the first terminal thereof.
2. The charge pump of claim 1 , wherein a size of the second transistor controls a voltage level of the output voltage.
3. The charge pump of claim 1 , further comprising:
a delay circuit for receiving the inverted version of the clock signal and generating a delayed inverted version of the clock signal; and
a first set of inverters connected to the delay circuit for receiving the delayed inverted version of the clock signal and generating the delayed version of the clock signal.
4. The charge pump of claim 3 , wherein the delay circuit includes a second set of inverters.
5. The charge pump of claim 3 , wherein the delay circuit is a skewed delay circuit, and wherein a falling time of the delayed inverted version of the clock signal is less than a rising time of the delayed inverted version of the clock signal.
6. The charge pump of claim 1 , wherein the first and second transistors are p-channel metal-oxide semiconductor (PMOS) transistors, and the third, fourth, and fifth transistors are n-channel metal-oxide semiconductor (NMOS) transistors.
7. A charge pump, comprising:
a control circuit for receiving a clock signal and an inverted version of the clock signal and generating a control signal and a first intermediate signal, wherein the control circuit comprises:
a first transistor having a first terminal for receiving a supply voltage and a gate terminal for receiving the clock signal;
a second transistor having a gate terminal for receiving the inverted version of the clock signal and a first terminal connected to a second terminal of the first transistor for generating the first intermediate signal;
a third transistor having a gate terminal connected to a first terminal thereof and a second terminal of the second transistor; and
a fourth transistor having a gate terminal connected to the second terminal of the first transistor for receiving the first intermediate signal, a first terminal connected to ground, and a second terminal connected to a second terminal of the third transistor for generating the control signal;
a fifth transistor having a first terminal connected to the control circuit for receiving the first intermediate signal, a gate terminal connected to the control circuit for receiving the control signal, and a second terminal for generating a second intermediate signal; and
a capacitor having a first terminal connected to the second terminal of the fifth transistor for receiving the second intermediate signal and a second terminal for receiving a delayed inverted version of the clock signal, wherein the capacitor generates an output voltage at the first terminal thereof.
8. The charge pump of claim 7 , wherein a size of the third transistor controls a voltage level of the output voltage.
9. The charge pump of claim 7 , further comprising:
a delay circuit for receiving the inverted version of the clock signal and generating an intermediate delayed inverted version of the clock signal; and
a first set of inverters connected to the delay circuit for receiving the intermediate delayed inverted version of the clock signal and generating the delayed inverted version of the clock signal.
10. The charge pump of claim 9 , wherein the delay circuit further comprises a second set of inverters.
11. The charge pump of claim 9 , wherein the delay circuit is a skewed delay circuit, and wherein a falling time of the intermediate delayed inverted version of the clock signal is less than a rising time of the intermediate delayed inverted version of the clock signal.
12. The charge pump of claim 7 , wherein the first, second, and fifth transistors are p-channel metal-oxide semiconductor (PMOS) transistors, and the third and fourth transistors are n-channel metal-oxide semiconductor (NMOS) transistors.