Method and apparatus for enabling temporal alignment of debug information

1. A signal processing device for communication within a signal processing system comprising a master node and multiple signal processing devices including the signal processing device, the master node including circuitry and being in communication with the multiple signal processing devices, the signal processing device comprising:

at least one processing core configured and arranged to execute computer program code and to transmit data across at least one data layer, including a data link layer;

at least one timestamp generation component, including circuitry, configured and arranged to generate at least one local timestamp value, and to provide the at least one local timestamp value;

a data link layer module, including circuitry, configured and arranged to receive the at least one local timestamp value for timestamping of data packets within the data link layer; and

at least one debug module, including circuitry, configured and arranged to:

receive the at least one local timestamp value and to cause temporal alignment of debug information across the multiple signal processing devices within the signal processing system by:

timestamping the debug information corresponding to the signal processing system based at least partly on the at least one local timestamp value and timing information obtained from the master node, and

outputting the timestamped debug information to a debug tool of the signal processing system.

2. The signal processing device of claim 1 , wherein the timing information includes system timing offset information that is indicative of an offset between the at least one local timestamp value and a system timing reference, wherein the at least one debug module is configured and arranged to obtain the system timing offset information corresponding to the at least one local timestamp value, and to output the timestamped debug information to an external debug tool, the timestamped debugged information being temporally aligned with debug information from the other signal processing devices of the plurality of the signal processing system located at different physical locations than the signal processing device.

3. The signal processing device of claim 2 , wherein the at least one debug module is configured and arranged to obtain the system timing offset information from a system synchronisation component of the signal processing system, the system sychronisation component configured and arranged to execute on at least one processing core of the signal processing device and to determine the system timing offset information from a master node timestamp value received from the master node.

4. The signal processing device of claim 2 , wherein the at least one debug module is configured and arranged to obtain system timing offset information from at least one memory element of the signal processing device.

5. The signal processing device of claim 2 , wherein the at least one debug module is configured and arranged to make the obtained system timing offset information available to an external debug tool.

6. The signal processing device of claim 2 , wherein the at least one debug module is configured and arranged to apply an offset to the at least one local timestamp value in accordance with the obtained system timing offset information and to timestamp the debug information based at least partly on the offset local timestamp value.

7. The signal processing device of claim 2 , wherein the timing offset information comprises precision time protocol.

8. The signal processing device of claim 1 , wherein the debug information comprises at least one of:

trace information;

breakpoint information;

watchpoint information; and

event information.

9. The signal processing device of claim 1 , wherein the at least one timestamp generation component is configured and arranged to provide the at least one local timestamp value to at least one media access controller (MAC) module for timestamping of data packets.

10. The signal processing device of claim 1 implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.

11. A signal processing system comprising at least one signal processing device according to claim 1 .

12. The signal processing device of claim 1 , the signal processing device further including a plurality of processing cores configured and arranged to execute computer program code, and wherein the at least one signal processing device configured and arranged within a server blade located within a server rack at a site of a plurality of sites of the signal processing system, and

wherein the at least one debug module is further configured and arranged to temporally align debug information for the plurality of processing cores with respect to one another by timestamping the debug information for the plurality of processing cores of the signal processing device.

13. The signal processing device of claim 1 , wherein the at least one debug module is further configured and arranged to provide system timing offset information to an external debug tool.

14. The signal processing device of claim 1 , further including at least one memory element configured and arranged to provide system timing offset information to an external debug tool.

15. The signal processing device of claim 1 , wherein the at least one signal processing device is configured and arranged to obtain system timing offset information corresponding to the at least one local timestamp value, and to generate the time stamp for the debug information that is aligned to a system timing reference using the at least one local timestamp value and the system timing offset information.

16. The signal processing device of claim 15 , wherein the system timing offset information includes a measure to indicate an extent to which the local timestamp value is offset from the system timing reference obtained from the master node and a network propagation delay between the signal processing device and the master node.

17. A method of enabling temporal alignment of debug information for a signal processing system, the method comprising, within a signal processing device:

transmitting data across at least one data link layer of the signal processing system using at least one processing core of the signal processing device;

receiving debug information using the signal processing device;

obtaining, using at least one timestamp generation circuitry of the signal processing device, a local timestamp value used for timestamping of data packets within the data link layer of the signal processing device;

timestamping, using at least one debug module including circuitry of the signal processing device, the received debug information based at least partially on the local timestamp value received from the at least one timestamp generation circuitry;

temporally aligning the timestamping of the debug information with a system timing reference, the system timing reference including a precision time protocol message indicative of a system reference time of the signal processing system;

receiving the precision time protocol message from a precision time protocol master node;

adjusting the local timestamp value based on the system timing reference;

timestamping the debug information and the data packets within the at least one data link layer with the adjusted local timestamp value; and

outputting the timestamped debug information to a debug tool of the signal processing system.

18. The method of claim 17 , further including:

timestamping the received debug information and the data packets within the data link layer of the signal processing device using the local timestamp value, and

outputting the timestamp debug information to an external debug tool, the timestamped debug information being temporally aligned with debug information from other signal processing devices of the signal processing system located at different physical locations than the signal processing device.