IP Library Granted Patent US 9,823,959
Granted Patent B2
US 9,823,959 · App. 14/889,476 · Granted Nov 21, 2017

Microcontroller unit and method of operating a microcontroller unit

Inventors: Vladimir Litovtchenko (Ebersberg, DE); Joachim Fader (Munich, DE); Harald Luepken (Zorneding, DE)
Assignee: NXP USA, Inc.
G06F11/0793G06F11/076G06F11/079G06F11/0721
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Quick Facts
Patent No.
US 9,823,959
App. No.
14/889,476
Granted
Nov 21, 2017
Kind
B2
Abstract

A microcontroller unit having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.

Claims (42)

1. A microcontroller unit comprising:

a functional state;

a reset state; and

one or more assertable fault sources, wherein

each fault source has its own fault source assertion count and its own fault source assertion limit, and

the MCU is arranged to cyclically

pass from the functional state to the reset state and increase the fault source assertion counts of the asserted fault sources by one increment if one or more of the fault sources are asserted,

disable the respective fault source for each fault source assertion count that exceeds the respective fault source assertion limit such that each disabled fault source cannot trigger the MCU to return to the reset state, and

pass from the reset state to the functional state.

2. The MCU of claim 1 , further arranged, in the functional state, to perform a debugging operation or a limited application run if one or more of the fault sources are disabled.

3. The MCU of claim 1 , further arranged, in the functional state, to perform the following for each of the fault sources: reset the corresponding fault source assertion count to an initial value if the respective fault source is not asserted.

4. The MCU of claim 1 , wherein the reset state is a safe state.

5. A microcontroller unit comprising:

a functional state;

a reset state; and

one or more assertable fault sources, wherein

each fault source has its own fault source assertion count and its own fault source assertion limit, and

the MCU is arranged to cyclically

pass from the functional state to the reset state and increase the fault source assertion counts of the asserted fault sources by one increment if one or more of the fault sources are asserted,

disable the respective fault source for each fault source assertion count that exceeds the respective fault source assertion limit, and

pass from the reset state to the functional state,

wherein the MCU is arranged to provide a reset count and to add the following operations to the cyclic sequence:

if the MCU passes from the functional state to the reset state, increase the reset count by one increment;

if the reset count matches a guarding window triggering number, prolong the period during which the MCU is in the reset state and reset the reset count to an initial value.

6. The MCU of claim 5 , wherein the MCU is arranged to provide a guarding window count and to add the following operations to the cyclic sequence:

in response to the reset count matching a guarding window triggering number, increase the guarding window count by one increment;

wherein the duration of said prolonged period is configurable to increase with the guarding window count.

7. The MCU of claim 6 , wherein the duration of said prolonged period is arranged to become infinite when the guarding window count exceeds a critical number.

8. A method of operating a microcontroller unit (MCU), wherein the MCU having a functional state, a reset state, and one or more assertable fault sources, each fault source has its own fault source assertion count and its own fault source assertion limit, the method comprising cyclically:

setting the MCU to the reset state and increasing the respective fault source assertion counts by one increment if one or more of the fault sources are asserted; and

for each fault source assertion count that exceeds the respective fault source assertion limit, disabling the corresponding fault source, such that each disabled fault source cannot trigger the MCU to return to the reset state; and

setting the MCU to the functional state.

9. A method of operating a microcontroller unit (MCU), wherein the MCU having a functional state, a reset state, and one or more assertable fault sources, each fault source has its own fault source assertion count and its own fault source assertion limit, the method comprising cyclically:

setting the MCU to the reset state and increasing the respective fault source assertion counts by one increment if one or more of the fault sources are asserted; and

for each fault source assertion count that exceeds the respective fault source assertion limit, disabling the corresponding fault source, and

setting the MCU to the functional state,

wherein the MCU is arranged to provide a reset count and further comprising cyclically:

if the MCU passes from the functional state to the reset state, increasing the reset count by one increment; and

if the reset count matches a guarding window triggering number, prolonging the period during which the MCU is in the reset state and resetting the reset count to an initial value.

10. The method of claim 9 , wherein the MCU is arranged to provide a guarding window count and further comprising cyclically:

in response to the reset count matching a guarding window triggering number, increasing the guarding window count by one increment, wherein the duration of said prolonged period is configurable to increase with the guarding window count.

11. The method of claim 10 , wherein the duration of said prolonged period becomes infinite when the guarding window count exceeds a critical number.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2015
From: LITOVTCHENKO, VLADIMIR; FADER, JOACHIM; LUEPKEN, HARALD
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036975/0953 →
Continuity (1)
Related Publication 20160124800A1 · May 5, 2016