IP Library Patent Application 14889497
Patent Application
App. No. 14/889,497

RECEIVER SYSTEM AND METHOD FOR RECEIVER TESTING

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Patent No.
US None
App. No.
14/889,497
Abstract

A receiver system which may be implemented in an integrated circuit device and suitable for use in automotive radar systems such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier and mixed in a down-conversion mixer with an RF test signal. The RF test signal is generated on the device by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. Baseband components may also be checked using test signals of suitable frequency divided down from the local oscillator test signal by a programmable frequency divider. This self test arrangement obviates any need for applying externally generated RF test signals to the IC device.

Claims (29)

1 . A receiver system comprising:

a down-conversion mixer;

a frequency multiplier configured to generate a local oscillator test signal;

a first coupler configured to couple the local oscillator test signal to a first input of the down-conversion mixer;

an input port configured to receive a test signal;

an up-conversion mixer configured to mix the received test signal with the local oscillator test signal to produce an RF test signal;

a second coupler configured to couple the RF test signal to a second input of the down-conversion mixer; and

an output port configured to receive a baseband signal from an output of the down-conversion mixer.

2 . The receiver system of claim 1 wherein the frequency multiplier comprises a phase-locked loop.

3 . The receiver system of claim 2 wherein the phase-locked loop is configured to be driven by a SPI (serial peripheral interface) clock signal.

4 . The receiver system of claim 1 wherein the frequency multiplier is configured to be driven by a SPI (serial peripheral interface) clock signal and arranged to multiply the SPI clock signal by harmonic multiplication.

5 . The receiver system of claim 1 further comprising:

a baseband module arranged between an output of the down-conversion mixer and the I F output port; and

a programmable frequency divider operably coupled to the output of the frequency multiplier and configured to generate baseband test signals for applying to the baseband components.

6 . The receiver system of claim 5 further comprising a switch configured to divert the received test signal to either the up-conversion mixer or to the baseband module.

7 . The receiver system of claim 1 implemented in an integrated circuit

8 . A method for testing a receiver, the method comprising:

generating in the receiver a local oscillator test signal using a frequency multiplier;

coupling the local oscillator test signal to a first input of a down-conversion mixer;

receiving a test signal at an input port of the receiver;

up-converting the received test signal with the local oscillator test signal in an up-conversion mixer to produce an RF test signal;

coupling the RF test signal to a second input of the down-conversion mixer; and

mixing the RF test and local oscillator test signals in the down-conversion mixer to produce a baseband signal at an output port of the receiver.

9 . The method of claim 8 comprising:

dividing the local oscillator test signal to produce lower frequency test signals; and

applying said lower frequency test signals to baseband components of the receiver

10 . The method of claim 9 wherein dividing the local oscillator test signal is performed in a programmable frequency divider

11 . The method according to claim 8 wherein the frequency multiplier comprises a phase-locked loop.

12 - 15 . (canceled)

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2015
From: DEHLINK, BERNHARD; GHAZINOUR, AKBAR; REUTER, RALF
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036976/0374 →