Method and apparatus for offloading functional data from an interconnect component
An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.
1. An interconnect offload component arranged to operate in at least an offloading mode in which the interconnect offload component is arranged to:
receive functional data from at least one interconnect client component of a signal processing device for communication to at least one destination component; and
forward at least a part of the received functional data to at least one debug network of the signal processing device for communication to the at least one destination component via the at least one debug network.
2. The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive functional data from the at least one interconnect client component for communication to at least one destination component;
determine whether the received functional data comprises non-coherent data; and
forward at least a part of the received functional data to the at least one debug network for communication to the at least one destination component if the at least part of the received functional data comprises non-coherent data.
3. The interconnect offload component of claim 2 , wherein the interconnect offload component is arranged to forward at least a part of the received functional data to the at least one interconnect component of the signal processing device for communication to the at least one destination component if the at least part of the received functional data comprises coherent data.
4. The interconnect offload component of claim 2 , wherein the interconnect offload component is arranged to determine whether the received functional data comprises non-coherent data based at least partly on a destination address for the received functional data.
5. The interconnect offload component of claim 4 , wherein the interconnect offload component is arranged to compare the destination address of the received functional data to at least one offload address and to determine whether the received functional data comprises non-coherent data based at least partly on said comparison.
6. The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive functional data from the at least one interconnect client component for communication to at least one destination component;
determine whether to forward at least a part of the received functional data to the at least one debug network for communication to the at least one destination component based at least partly on a set of rules; and
forward at least a part of the received functional data to the at least one debug network for communication to the at least one destination component if so determined.
7. The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive at least one direct memory access transaction from at least one direct memory access component of the signal processing device for communication to at least one memory component; and
forward at least a part of the received direct memory access transaction to the at least one debug network of the signal processing device for communication to the at least one memory component via the at least one debug network.
8. The interconnect offload component of claim 1 , wherein the interconnect offload component is arranged to, when operating in the offloading mode:
receive at least one data packet comprising functional data from the at least one interconnect client component for communication to at least one destination component;
forward a received payload component of the at least one data packet to the at least one debug network for communication to the at least one destination component; and
forward a header component of the received at least one data packet to the at least one interconnect component for communication to the at least one destination component.
9. The interconnect offload component of claim 1 , wherein the interconnect offload component is configurable to enable and disable the offloading mode; the interconnect offload component being arranged to forward the received functional data to the at least one interconnect component of the signal processing device upon the offloading mode being disabled.
10. An integrated circuit device comprising at least one die within a single integrated circuit package, comprising an interconnect offload component arranged to operate in at least an offloading mode in which the interconnect offload component is arranged to:
receive functional data from at least one interconnect client component of a signal processing device for communication to at least one destination component; and
forward at least a part of the received functional data to at least one debug network of the signal processing device for communication to the at least one destination component via the at least one debug network.