Gate drive circuit and a method for controlling a power transistor
View Patent ↗A gate drive circuit to drive a gate terminal of a power transistor. The gate drive circuit includes a first capacitor, a first switch, a measurement circuit and a reference source to generate a reference voltage. The first capacitor has a first terminal electrically coupled to the gate terminal of the power transistor. The first switch is arranged between a second terminal of the first capacitor and a first predetermined voltage. The measurement circuit is used to measure a differential voltage across the first capacitor. The gate drive circuit is configured to pre-charge the first capacitor to obtain a second predetermined voltage across the first capacitor. The gate drive circuit is further configured to arrange the first switch in an on state to turn on the power transistor and to electrically couple the first predetermined voltage to the second terminal of the first capacitor. The first capacitor is initially pre-charged at the second predetermined voltage.
1. A gate drive circuit for a power transistor, the gate drive circuit comprising:
a first capacitor, a first terminal of the first capacitor being electrically coupled to a gate terminal of the power transistor,
a first switch being arranged between a second terminal of the first capacitor and a first predetermined voltage,
a measurement circuit for measuring a differential voltage across the first capacitor,
a reference source for generating a reference voltage,
the gate drive circuit being configured to pre-charge the first capacitor to obtain a second predetermined voltage across the first capacitor, the gate drive circuit being further configured to arrange the first switch in an on state for turning on the power transistor to electrically couple the first predetermined voltage to the second terminal of the first capacitor being pre-charged at the second predetermined voltage, the measurement circuit being configured to arrange the first switch in an off state when the differential voltage across the first capacitor has changed with respect to the second predetermined voltage by the reference voltage.
2. The gate drive circuit as claimed in claim 1 wherein the second predetermined voltage is dependent on the reference voltage.
3. The gate drive circuit as claimed in claim 2 wherein the second predetermined voltage is a linear combination of a boost voltage and the reference voltage.
4. The gate drive circuit as claimed in claim 3 wherein the measurement circuit is configured to arrange the first switch in an off state when the differential voltage across the first capacitor has reached the boost voltage.
5. The gate drive circuit according to claim 2 , the gate drive circuit further comprising a switchable reference source and a pre-charge circuit, the switchable reference source comprising the reference source, the switchable reference source being arranged to be electrically coupled to the first terminal of the first capacitor, the switchable reference source being configured i) to electrically connect the reference source to the first terminal of the first capacitor during the pre-charge of the first capacitor, and ii) to electrically disconnect the reference source from the first terminal of the first capacitor after the pre-charge of the first capacitor, and the pre-charge circuit being configured to generate a boost voltage at the second terminal of the first capacitor during the pre-charge of the first capacitor.
6. The gate drive circuit according to claim 5 wherein the pre-charge circuit comprises a voltage limiter and a second switch, a first terminal of the voltage limiter being electrically coupled to the second terminal of the first capacitor, a second terminal of the voltage limiter being electrically coupled to a reference potential by means of the second switch, the gate driver circuit being configured i) to arrange the second switch in an on state during the pre-charge of the first capacitor and ii) to arrange the second switch in an off state after the pre-charge of the capacitor.
7. The gate drive circuit according to claim 6 wherein the measurement circuit is a comparator, a first input of the comparator being electrically coupled to the second terminal of the voltage limiter, a second input of the comparator being electrically coupled to the first terminal of the first capacitor.
8. The gate drive circuit according to claim 7 further comprising a set-reset flip flop, an output of the set-reset flip flop being electrically coupled to the first switch for controlling the first switch, a reset input of the set-reset flip flop being electrically coupled to an output of the comparator, the reset input being configured to receive a signal from the comparator ( 10 ) for arranging the first switch in an off state, a set input of the set-reset flip flop being configured to receive a signal for arranging the first switch in an on state.
9. The gate drive circuit according to claim 6 wherein the gate drive circuit further comprises a third switch being arranged between the second terminal of the first capacitor and the reference potential to electrically couple the second terminal to the reference potential when the third switch is on.
10. The gate drive circuit according to claim 9 wherein the first switch, the second switch and the third switch are N channel field effect transistors.
11. The gate drive circuit according to claim 1 further comprising a second capacitor, a first terminal of the second capacitor being electrically coupled to the second terminal of the first capacitor, a second terminal of the second capacitor being electrically coupled to a control terminal of the first switch.
12. The gate drive circuit as claimed in claim 1 wherein the first predetermined voltage (Vp 1 ) is larger than the second predetermined voltage.
13. The gate drive circuit according to claim 1 wherein the power transistor is an IGBT.
14. A power inverter comprising:
a first capacitor, a first terminal of the first capacitor-being electrically coupled to a gate terminal of a power transistor,
a first switch being arranged between a second terminal of the first capacitor and a first predetermined voltage,
a measurement circuit for measuring a differential voltage across the first capacitor,
a reference source for generating a reference voltage,
a gate drive circuit being configured to pre-charge the first capacitor to obtain a second predetermined voltage across the first capacitor, the gate drive circuit being further configured to arrange the first switch in an on state for turning on the power transistor to electrically couple the first predetermined voltage to the second terminal of the first capacitor being pre-charged at the second predetermined voltage, the measurement circuit being configured to arrange the first switch in an off state when the differential voltage across the first capacitor has changed with respect to the second predetermined voltage by the reference voltage,
the power inverter further comprising a further power transistor, a gate terminal of the further power transistor electrically coupled to a further gate drive circuit, an emitter or source terminal of the further power transistor being electrically coupled to the collector terminal of the power transistor and a collector or drain terminal of the further power transistor being electrically coupled to a supply voltage.
15. A method for controlling a power transistor, the method comprising:
providing a first switch between a first capacitor and a first predetermined voltage, a first terminal of the first capacitor connected to a gate terminal of the power transistor,
pre-charging the first capacitor to obtain a second predetermined voltage across the first capacitor,
arranging the first switch in an on state to electrically couple the first predetermined voltage to the a second terminal of the first capacitor,
measuring a differential voltage across the first capacitor by means of a measuring circuit,
arranging the first switch in an off state if the differential voltage across the first capacitor has changed with respect to the second predetermined voltage by a reference voltage.
16. The method of claim 15 further comprising after arranging the first switch in an off state:
arranging a third switch in an on state to electrically couple the second terminal of the first capacitor to a reference potential,
arranging the third switch in an off state and the first switch in an on state to re-charge the first capacitor.