IP Library Granted Patent US 9,952,922
Granted Patent B2
US 9,952,922 · App. 14/899,595 · Granted Apr 24, 2018

Fault detection apparatus and method

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Quick Facts
Patent No.
US 9,952,922
App. No.
14/899,595
Granted
Apr 24, 2018
Kind
B2
Abstract

Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

Claims (26)

1. A method for detecting a fault in a device, the method comprising;

receiving from the device, a first signal to be monitored, said first signal to be monitored having a value;

generating a first hash index key for the first signal to be monitored;

searching, using said generated first hash index key, a hash table for an entry matching the value of the received first signal;

if a matching entry is not found, completing a first action; and

if a matching entry is found, completing a second action associated with the found matching entry, wherein the second action comprises:

enabling a first timer and a second timer, wherein a time interval of the second timer is longer than a time interval of the first timer;

receiving a second signal to be monitored;

said second signal having a value;

generating a second hash index key for said second signal;

searching, using the generated second hash index key, the hash table for an entry matching the value of the received second signal,

generating a fault notification signal in response to an entry matching the value of the received second signal being found before the first timer expires; and

generating the fault notification signal in response to the second timer expiring before an entry matching the value of the received second signal is found.

2. The method of claim 1 , wherein said first action comprises generating the fault notification signal.

3. The method of claim 1 wherein said first action comprises putting the device into a failsafe mode of operation.

4. The method of claim 1 wherein the timer sets one or more predetermined time intervals and if no matching entry is found within a time interval set by the timer, completing a third action.

5. The method of claim 4 wherein the third action comprises generating a fault notification signal.

6. The method of claim 4 wherein the third action comprises putting the device into a failsafe mode of operation.

7. The method of claim 4 wherein the third action comprises generating an interrupt.

8. Fault detection apparatus to detect a fault in a device, said apparatus comprising:

a memory to store a hash table, and

a monitor circuit arranged to receive from the device, a signal to be monitored, said signal to be monitored having a value, to generate a first hash index key for the signal to be monitored, to search, via said generated first hash index key, the hash table for an entry matching the value of the received signal, and if a matching entry is not found, to complete a first action and if a matching entry is found, to complete a second action associated with the found matching entry, wherein the second action comprises: the monitor circuit to enable a first timer and a second timer, wherein a time interval of the second timer is longer than a time interval of the first timer, to receive a second signal to be monitored, said second signal having a value, to generate a second hash index key for said second signal, to search, using the generated second hash index key, the hash table for an entry matching the value of the received second signal, to generate a fault notification signal in response to an entry matching the value of the received second signal being found before the first timer expiring before, and to generate the fault notification signal in response to the second timer expiring before an entry matching the value of the received second signal is found.

9. The fault detection apparatus of claim 8 comprising the first and second timer arranged to set one or more predetermined time intervals during which the hash table is searched for a matching entry.

10. The fault detection apparatus of claim 8 wherein the fault detection apparatus is implemented in one or more integrated circuit devices.

11. A non-transitory tangible computer program product having executable program code stored thereon for execution by a processor to perform a method in accordance with claim 1 .

12. The tangible computer program product of claim 11 wherein the tangible computer program product comprises at least one from a group consisting of: a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a Read Only Memory, a Programmable Read Only Memory, an Erasable Programmable Read Only Memory, EPROM, an Electrically Erasable Programmable Read Only Memory and a Flash Memory.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2018
From: EDMISTON, GRAHAM; DEVINE, ALAN; MCMENAMIN, DAVID; ROBERSTON, ANDREW; SCOBIE, JAMES ANDREW COLLIER
To: NXP USA, INC.; FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 045178/0078 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2015
From: EDMISTON, GRAHAM; DEVINE, ALAN; MCMENAMIN, DAVID; ROBERSTON, ANDREW
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037323/0720 →