Non-volatile memory (NVM) cell and a method of making

1. A method of forming a flash memory cell comprising:

forming a first hard mask and a second hard mask on a substrate;

forming a select gate as a spacer around the first hard mask;

forming a charge storage layer over the first and second hard masks and the select gate;

forming a control gate over the charger storage layer, the control gate formed as a spacer around the second hard mask; and

filling a recess in the control gate with a dielectric material, the recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

2. The method of claim 1 further comprising:

chemically-mechanically polishing the dielectric material, the select gate, the charge storage layer, and the control gate.

3. The method of claim 1 , wherein:

the forming the select gate as the spacer includes using a spacer etch.

4. The method of claim 1 , wherein:

the forming the control gate as the spacer includes using a spacer etch.

5. The method of claim 4 further comprising:

removing the first and second hard mask.

6. The method of claim 5 further comprising:

removing a portion of the charge storage layer adjacent a top portion of a curved sidewall of the select gate.

7. A method comprising:

forming a first and second hard mask on a semiconductor substrate, the first and second hard masks are separated from each other by more than a desired channel length for a flash memory cell;

depositing a layer of polysilicon material over and between the first and second hard masks;

etching the layer of polysilicon material to form select gates around the first and second hard masks;

masking the first hard mask and the select gate around the first hard mask;

removing the select gate around the second hard mask;

unmasking the first hard mask and the select gate around the first hard mask;

forming a charge storage layer over the first and second hard masks and the select gate around the first hard mask;

depositing another layer of polysilicon material over the charge storage layer and the select gate and the first and second hard mask; and

etching the other layer of polysilicon material to form a control gate around the second hard mask, wherein the select gate, the charge storage layer and the control gate are part of the flash memory cell.

8. The method of claim 7 further comprising:

filling a space between a sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the sidewall of the control gate with a dielectric material.

9. The method of claim 8 further comprising:

chemically-mechanically polishing the dielectric material, the select gate, the charge storage layer and the control gate to remove portions of the charge storage layer over the first and second hard masks.

10. The method of claim 7 wherein the forming the charge storage layer includes:

growing a thermal oxide;

depositing a charge storage material over the thermal oxide; and

depositing a dielectric material over the charge storage material.

11. The method of claim 10 further comprising:

the charge storage material comprises one of a group consisting of nanocrystals and a layer of nitride.