IP Library Granted Patent US 9,577,084
Granted Patent B2
US 9,577,084 · App. 14/981,831 · Granted Feb 21, 2017

Semiconductor device having a semiconductor layer stacked body

Inventors: Masahiro Hikita (Hyogo, JP); Hideyuki Okita (Toyama, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L29/7787H01L29/1066H01L29/205H01L29/207H01L29/66462H01L29/7786H01L29/2003
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Quick Facts
Patent No.
US 9,577,084
App. No.
14/981,831
Granted
Feb 21, 2017
Kind
B2
Abstract

A semiconductor device includes a substrate, a semiconductor layer stacked body, and a source electrode and a drain electrode formed on the semiconductor layer stacked body. The semiconductor layer stacked body includes a first nitride semiconductor layer formed on the substrate, and a second nitride semiconductor layer formed on the first nitride semiconductor layer. The semiconductor device further includes a third nitride semiconductor layer formed on the second nitride semiconductor layer and disposed between the source electrode and the drain electrode, and a gate electrode formed on the third nitride semiconductor layer. The semiconductor device includes a first magnesium-containing region having a magnesium concentration of 1×10 18 cm −3 or more that is provided right under the third nitride semiconductor layer, from an upper surface of the second nitride semiconductor layer to a position lower than an interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

Claims (24)

1. A semiconductor device comprising:

a substrate;

a semiconductor layer stacked body including a first nitride semiconductor layer formed on the substrate, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher bandgap energy than the first nitride semiconductor layer;

a source electrode and a drain electrode formed on the semiconductor layer stacked body;

a third nitride semiconductor layer of p-type formed on the second nitride semiconductor layer, and disposed between the source electrode and the drain electrode; and

a gate electrode formed on the third nitride semiconductor layer, wherein

a first magnesium-containing region having a magnesium concentration of 1×10 18 cm −3 or more is provided right under the third nitride semiconductor layer, from an upper surface of the second nitride semiconductor layer to a position lower than an interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

2. The semiconductor device according to claim 1 , wherein

a lower surface of the first magnesium-containing region reaches a position lower than the interface between the first nitride semiconductor layer and the second nitride semiconductor layer by a distance of 1 nm or more and 10 nm or less.

3. The semiconductor device according to claim 1 , wherein

the magnesium concentration of the first magnesium-containing region is 1×10 19 cm −3 or less.

4. The semiconductor device according to claim 1 , wherein

a recess is formed in the upper surface of the second nitride semiconductor layer, right under the third nitride semiconductor layer, and the recess is filled with the third nitride semiconductor layer.

5. The semiconductor device according to claim 4 , wherein

a magnesium is contained in the second nitride semiconductor layer except for a region right under the recess at a magnesium concentration of 1×10 18 cm −3 or more, from the upper surface of the second nitride semiconductor layer to a depth which is equal to a depth of the first magnesium-containing region right under the third nitride semiconductor layer.

6. A semiconductor device comprising:

a substrate;

a semiconductor layer stacked body including a first nitride semiconductor layer having a recess, a second nitride semiconductor layer having a higher bandgap energy than the first nitride semiconductor layer and formed on the first nitride semiconductor layer except for the recess, and a fourth nitride semiconductor layer stacked so as to cover the first and second nitride semiconductor layers including an inner wall of the recess, and having a higher bandgap energy than the first nitride semiconductor layer, wherein the first, second, and fourth nitride semiconductor layers are sequentially formed on the substrate;

a third nitride semiconductor layer of p-type formed on the fourth nitride semiconductor layer at a place above the recess;

a gate electrode formed on the third nitride semiconductor layer; and

a source electrode and a drain electrode formed on the semiconductor layer stacked body at each of both sides of the third nitride semiconductor layer, respectively, wherein

magnesium is added to the fourth nitride semiconductor layer.

7. The semiconductor device according to claim 6 , wherein

the recess has a depth of 1 nm or more.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069503/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2016
From: HIKITA, MASAHIRO; OKITA, HIDEYUKI
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 037495/0841 →
Priority Claims (1)
JP 2013-147246 · Jul 16, 2013 · national
Continuity (2)
Continuation PCTJP2014003234 · Jun 17, 2014
Related Publication 20160118489A1 · Apr 28, 2016