Convex shaped thin-film transistor device having elongated channel over insulating layer in a groove of a semiconductor substrate
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines and an insulating layer that is provided between the first bit lines and in a groove. First faces of the first bit lines are aligned on a first line and second faces of the first bit lines are aligned on a second line. A first face of the insulating layer is disposed at a third line that is a first distance from the first line in a first direction and a second face of the insulating layer is disposed at a fourth line that is a second distance from the second line in a second direction.
1. A semiconductor device comprising:
a substrate;
a plurality of first bit lines comprising a plurality of upper surfaces and a plurality of lower surfaces, wherein the plurality of first bit lines are disposed to align the plurality of upper surfaces substantially in a first plane and to align the plurality of lower surfaces substantially in a second plane;
an insulating layer that is provided between the plurality of first bit lines, the insulating layer comprising an upper surface and a lower surface, wherein at least a portion of the lower surface of the insulating layer is provided in a groove of the semiconductor device, wherein the groove is disposed substantially in a third plane below the second plane and the upper surface is substantially in a fourth plane above the first plane; and
an ONO film comprising an oxide film, a tunnel oxide film, and a plurality of charge storage layers, and
a plurality of channel layers provided on opposing third and fourth faces of the insulating layer and coupled to the respective first bit lines of the plurality of first bit lines,
wherein at least a portion of the ONO film is formed on a portion of the plurality of channel layers and at least a portion of a first face of the oxide film is in direct contact with a first face of the tunnel oxide film; and
wherein a path of a current flowing through the substrate and between the plurality of first bit lines is lengthened by the portion of the insulating layer provided in the groove.
2. The semiconductor device of claim 1 , wherein the channel layers are coupled to each other on the insulating layer to form one channel layer.
3. The semiconductor device of claim 1 , further comprising a second bit line that is provided on the insulating layer and is coupled to the plurality of channel layers.
4. The semiconductor device of claim 3 , wherein two charge storage layers of the plurality of charge storage layers are formed at a portion of the ONO film between a first bit line and a second bit line.
5. The semiconductor device of claim 1 , wherein a pair of charge storage layers of the plurality of charge storage layers are physically separated by the first face of the tunnel oxide film.
6. The semiconductor device of claim 1 , wherein the plurality of channel layers comprises a plurality of polysilicon layers.
7. The semiconductor device of claim 1 , wherein the plurality of charge storage layers comprises a plurality of silicon nitride films.
8. The semiconductor device of claim 1 , further comprising a plurality of word lines perpendicular to the plurality of first bit lines, the oxide film being interposed between the plurality of word lines and the plurality of charge storage layers.
9. The semiconductor device of claim 8 , wherein at least a portion of the plurality of word lines comprises a gate.
10. The semiconductor device of claim 8 , further comprising:
an interlayer insulating film,
a plurality of wiring layers; and
a protection film, wherein the interlayer insulating film, the plurality of wiring layers, and the protection film are provided over the plurality of word lines.
11. The semiconductor device of claim 10 , wherein the semiconductor device comprises a flash memory device.
12. The semiconductor device of claim 11 , wherein the plurality of charge storage layers comprises a plurality of floating gates.
13. The semiconductor device of claim 11 , wherein the plurality of charge storage layers are formed on the opposing third and fourth faces of the insulating layer according to a sidewall technique.
14. The semiconductor device of claim 11 , wherein the plurality of charge storage layers are formed by isolating two portions of a single contiguous charge storage layer from each other via etching.
15. The semiconductor device of claim 11 , wherein the charge storage layers of the plurality of charge storage layers are physically separated by the first face of the tunnel oxide.
16. The semiconductor device of claim 1 , wherein the insulating layer comprises faces oblique with respect to a face of the substrate.
17. The semiconductor device of claim 1 , wherein a punch through condition is substantially prevented by the portion of the insulating layer provided in the groove.