Phase locked loop circuit, integrated circuit, communication unit and method therefor
A phase locked loop circuit includes a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO.
1. A phase locked loop, PLL, circuit comprising:
a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage;
a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage;
a loop filter having an input and an output;
a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO; and
a logic inverter coupled to an output of the phase detector and an input of the level shifter circuit and configured to pre-compensate for a pulse inversion caused by the level shifter circuit;
wherein the level shifter comprises a transistor coupled to a resistive divider configured to set the level shift to be applied to the phase difference pulse signal.
2. The phase locked loop circuit of claim 1 , wherein the level shifter circuit is configured to convert in a non-linear manner a change in a duty cycle of the phase difference pulse signal into the averaged signal to the VCO.
3. The phase locked loop circuit of claim 1 , wherein the level shifter circuit is configured to generate a variable phase detector gain that compensates a variable VCO gain such that a product of the variable phase detector gain and variable VCO gain is constant.
4. The phase locked loop circuit of claim 1 , wherein the level shifter circuit applies a level shift such that the phase difference pulse signal approaches or reaches a maximum oscillator tuning voltage (V tune ).
5. The phase locked loop circuit of claim 1 , wherein the phase detector is an exclusive-OR circuit in a first order PLL.
6. The phase locked loop circuit of claim 1 , wherein at least one resistive element of the resistive divider is coupled to at least one capacitive element to form a loop filter input to the VCO, thereby providing continuous VCO frequency tuning voltage.
7. The phase locked loop circuit of claim 1 , wherein the transistor is a common emitter transistor stage switched by the phase difference pulse signal output from the phase detector and at least one resistive element of the resistive divider is coupled to a collector port of the common emitter transistor stage.
8. The phase locked loop circuit of claim 1 , wherein the transistor is a common source transistor stage switched by the phase difference pulse signal output from the phase detector and at least one resistive element of the resistive divider is coupled to a drain port of the common source transistor stage.
9. A phase locked loop, PLL, circuit comprising:
a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage;
a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage;
a loop filter having an input and an output; and
a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO;
wherein the level shifter circuit comprises a transistor coupled to a resistive divider configured to set the level shift to be applied to the phase difference pulse signal; and
wherein the transistor is provided with a supply voltage, Vcc 2 , via a first resistive element, R 1 , of the resistive divider, the phase detector includes two inputs with a phase difference there between, and a transistor output to the VCO is provided via a second resistive element, R 2 , of the resistive divider, such that an oscillator tuning voltage, V tune , is given by:
Vtune
≈
Vcc
2
×
R
2
R
1
+
R
2
×
phase_difference
π
1
-
R
1
R
1
+
R
2
×
phase_difference
π
.
10. An integrated circuit for a phase locked loop, PLL, comprising:
a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with an oscillator tuning voltage; and
a loop filter having an input and an output;
a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate voltage controlled oscillator, VCO, gain and the loop filter averages the phase difference pulse signal to output an averaged signal to a VCO; and
a logic inverter coupled to an output of the phase detector and an input of the level shifter circuit and configured to pre-compensate for a pulse inversion caused by the level shifter circuit;
wherein the level shifter circuit comprises a transistor coupled to a resistive divider configured to set the level shift to be applied to the phase difference pulse signal.
11. The integrated circuit of claim 10 , wherein the level shifter circuit is configured to convert in a non-linear manner a change in a duty cycle of the phase difference pulse signal into the averaged signal to the VCO.
12. The integrated circuit of claim 10 , wherein the level shifter circuit is coupled to the loop filter and phase detector and configured to generate a variable phase detector gain that compensates a variable VCO gain such that a product of the variable phase detector gain and variable VCO gain is constant.
13. The integrated circuit of claim 10 , wherein the level shifter circuit applies a level shift such that the phase difference pulse signal approaches or reaches a maximum oscillator tuning voltage, V tune .
14. The integrated circuit of claim 10 , wherein the phase detector is an exclusive-OR circuit in a first order PLL.
15. The integrated circuit of claim 10 , wherein at least one resistive element of the resistive divider is coupled to at least one capacitive element to form a loop filter input to the VCO, thereby providing continuous VCO frequency tuning voltage.
16. The integrated circuit of claim 10 , wherein the transistor is a common emitter transistor stage switched by the phase difference pulse signal output from the phase detector and at least one resistive element of the resistive divider is coupled to a collector port of the common emitter transistor stage.
17. A communication unit including a phase locked loop circuit comprising:
a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage;
a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage;
a loop filter having an input and an output; and
a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output provides an averaged signal to the VCO; and
a logic inverter coupled to an output of the phase detector and an input of the level shifter circuit and configured to pre-compensate for a pulse inversion caused by the level shifter circuit;
wherein the level shifter circuit comprises a transistor coupled to a resistive divider configured to set the level shift to be applied to the phase difference pulse signal.
18. A method of compensating in a phase locked loop, PLL, the method comprising:
applying a reference voltage and a PLL feedback signal to a phase detector;
outputting from the phase detector a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage to a logic inverter and from the logic inverter to a level shifter, the logic inverter being configured to pre-compensate for a pulse inversion caused by the level shifter;
inputting, to a voltage controlled oscillator, VCO, a level shifted representation of the phase difference pulse signal such that the level shift is configured to compensate VCO gain; and
averaging by a loop filter the phase difference pulse signal to output an averaged signal to the VCO;
wherein the level shifter comprises a transistor coupled to a resistive divider configured to set the level shift to be applied to the phase difference pulse signal.