Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators

1. A negative-capacitance apparatus comprising:

a first node coupled to a drain of a first transistor and a gate of a second transistor;

a second node coupled to a drain of the second transistor and a gate of the first transistor;

a capacitor coupled between a source of the first transistor and a source of the second transistor;

a first current mirror coupled between a supply voltage and the source of the first transistor; and

a second current mirror coupled between the supply voltage and the source of the second transistor.

2. The apparatus recited in claim 1 , further comprising a first amplifier that generates a differential signal coupled to the first and second nodes.

3. The apparatus recited in claim 2 , wherein the first amplifier is a programmable gain amplifier.

4. The apparatus recited in claim 2 , further comprising a plurality of amplifiers that are driven by the differential signal coupled to the first and second node.

5. The apparatus recited in claim 4 , wherein each of the plurality of amplifiers comprises a pre-amplifier of a comparator.

6. The apparatus recited in claim 4 , wherein a coupling is formed between the first amplifier and the plurality of amplifiers.

7. The apparatus recited in claim 5 , wherein the pre-amplifier of the comparator is a clock-less pre-amplifier.

8. The apparatus recited in claim 5 , wherein the pre-amplifier stages are abutted to one another such that an active transistor of a first differential stage in a first pre-amplifier stage behaves as a dummy transistor for an adjacent differential stage in a second pre-amplifier stage.

9. A method of increasing a transfer bandwidth of a differential signal comprising:

amplifying a differential input signal to provide the differential signal driving a differential capacitive load between a first and a second node;

coupling the first node to a drain of a first transistor and a gate of a second transistor;

coupling the second node to a drain of the second transistor and a gate of the first transistor;

coupling a capacitor between a source of the first transistor and a source of the second transistor;

coupling a first current mirror between a supply voltage and the source of the first transistor;

coupling a second current mirror between the supply voltage and the source of the second transistor; and

causing the differential capacitive load to be driven in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.

10. The method recited in claim 9 , wherein a first amplifier generates the differential input signal and a plurality of amplifiers receive the differential input signal.

11. The method recited in claim 10 , wherein the differential capacitive load comprises a differential capacitance of a differential interconnect, a differential input capacitance of the plurality of amplifiers, and a differential drain capacitance of the first amplifier.

12. The method recited in claim 10 , wherein the first amplifier is a programmable gain amplifier.

13. The method recited in claim 10 , wherein each of the plurality of amplifiers is a clock-less pre-amplifier of a comparator.

14. The method recited in claim 13 , further comprising abutting a plurality of clock-less pre-amplifier stages to one another such that an active transistor of a first differential stage in a first clock-less pre-amplifier stage behaves as a dummy transistor for an adjacent differential stage in a second clock-less pre-amplifier stage.

15. An apparatus comprising:

a first amplifier coupled to a first and a second node;

a differential capacitive load coupled to the first and the second node;

the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit;

a current mirror coupled to a source of each transistor; and

a capacitor coupled between the sources of the transistors.

16. The apparatus recited in claim 15 , further comprising a plurality of amplifiers coupled to the first and the second node.

17. The apparatus recited in claim 16 , further comprising a differential signal of the first amplifier drives the first and the second node.

18. The apparatus recited in claim 17 , wherein each of the plurality of amplifiers comprises a clock-less pre-amplifier of a comparator.

19. The apparatus recited in claim 17 , wherein the first amplifier is a programmable gain amplifier.

20. The apparatus recited in claim 18 , wherein the pre-amplifier stages are abutted to one another such that an active transistor of a first differential stage in a first pre-amplifier stage behaves as a dummy transistor for an adjacent differential stage in a second pre-amplifier stage.

21. An apparatus comprising a programmable gain amplifier (PGA) loaded by a plurality of analog to digital convertors (ADC's), comprising:

a differential output of the PGA coupled to a differential interconnect;

a differential input of each of the plurality of ADC's coupled to the differential interconnect; and

a negative-capacitance circuit coupled to the differential interconnect, wherein the negative-capacitance circuit comprises:

a first transistor cross-coupled to a second transistor with a capacitor coupling their sources together;

a first current source coupled to the first transistor; and

a second current source coupled to the second transistor.

22. The apparatus recited in claim 21 , wherein the first current source and the second current source have equivalent characteristics.

23. The apparatus recited in claim 21 , further comprising a control circuit configured to control the first current source and the second current source.

24. The apparatus recited in claim 23 , wherein the control circuit is configured to adjust a current of the first and the second current source to improve bandwidth response of the PGA.

25. The apparatus recited in claim 23 , wherein the control circuit comprises at least one of a digital control and an analog control.