ESD protection circuit having clamp control loop
Electrostatic discharge (ESD) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. A delay circuit is coupled to receive an output signal from the trigger circuit. The delay circuit includes a first inverter coupled to the input of the delay circuit and a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter. A clamp driver circuit is coupled to the output of the delay circuit.
1. An integrated circuit comprising:
a trigger circuit between a first power supply bus and a second power supply bus;
a delay circuit having an input coupled to receive an output signal from the trigger circuit and an output, the delay circuit including:
a first inverter having an input and an output, the input coupled to the input of the delay circuit;
a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter; and
a second capacitive element having a first terminal coupled to the first power supply bus and a second terminal coupled to the output of the first inverter; and
a clamp driver circuit having an input coupled to the output of the delay circuit, and an output.
2. The integrated circuit of claim 1 , further comprising a clamp transistor having a control electrode coupled to the output of the clamp driver circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the second power supply bus.
3. The integrated circuit of claim 1 , wherein the trigger circuit includes a first capacitive element and a first resistive element coupled in series between the first power supply bus and the second power supply bus.
4. The integrated circuit of claim 3 , wherein the delay circuit further includes a second inverter, the second inverter having an input coupled to the output of the first inverter, and an output coupled to the control terminal of the feedback transistor and to the output of the delay circuit.
5. The integrated circuit of claim 4 , wherein the first inverter includes a first P-channel transistor and a first N-channel transistor coupled in series, and the second inverter includes a second P-channel transistor and a second N-channel transistor coupled in series, and wherein a drive strength of the first N-channel transistor is less than a drive strength of the feedback transistor.
6. The integrated circuit of claim 5 , wherein the feedback transistor is characterized as a P-channel transistor, and wherein the first N-channel transistor has a width approximately one-half or less of the width of the feedback transistor.
7. The integrated circuit of claim 5 , further comprising a third N-channel transistor coupled between the second N-channel transistor and the second power supply bus, a control electrode of the third N-channel transistor coupled to a common node between the first capacitive element and the first resistive element.
8. The integrated circuit of claim 1 , wherein the clamp driver circuit further comprises a third P-channel transistor and a second resistive element coupled in series between the first power supply bus and the second power supply bus.
9. The integrated circuit of claim 1 , further comprising a fourth N-channel transistor and a fifth N-channel transistor coupled in series between the first power supply bus and the output of the delay circuit, control electrodes of the fourth and fifth N-channel transistors coupled to the output of the first inverter.
10. The integrated circuit of claim 9 , further comprising a third capacitive element having a first terminal coupled to the output of the delay circuit, and a second terminal coupled to the second power supply bus.
11. The integrated circuit of claim 10 , further comprising a third resistive element having a first terminal coupled to the first power supply bus, and a second terminal coupled to the input of the delay circuit.
12. An integrated circuit comprising:
a trigger circuit coupled between a first power supply bus and a second power supply bus, the trigger circuit including a first capacitive element and a first resistive element coupled in series between the first power supply bus and the second power supply bus;
a delay circuit having an input coupled to receive an output signal from the trigger circuit and an output, the delay circuit including:
a first inverter having an input coupled to the input of the delay circuit and an output, the first inverter including a first P-channel transistor and a first N-channel transistor coupled in series between the first power supply bus and the second power supply bus;
a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter; and
a second capacitive element having a first terminal coupled to the first power supply bus, and a second terminal coupled to the output of the first inverter; and
a clamp driver circuit having an input coupled to the output of the delay circuit, and an output.
13. The integrated circuit of claim 12 , further comprising a clamp transistor having a control electrode coupled to the output of the clamp driver circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the second power supply bus.
14. The integrated circuit of claim 12 , wherein the delay circuit further includes a second inverter, the second inverter including a second P-channel transistor and a second N-channel transistor coupled in series between the first power supply bus and a first current electrode of an N-channel enable transistor, the control electrode of the enable transistor coupled to a common node between the first capacitive element and the first resistive element.
15. The integrated circuit of claim 14 , wherein the trigger circuit further comprises a third inverter having an input coupled to the common node between the first capacitive element and the first resistive element, and an output coupled to the output of the trigger circuit, the third inverter including a third P-channel transistor and a third N-channel transistor coupled in series between the first power supply bus and the second power supply bus.
16. The integrated circuit of claim 12 , wherein the feedback transistor is characterized as a P-channel transistor, and wherein a length of the first N-channel transistor is approximately twice or more than a length of the feedback transistor.
17. The integrated circuit of claim 13 , wherein the clamp driver circuit further includes a P-channel driver transistor and a second resistive element coupled in series between the first power supply bus and the second power supply bus, a control electrode of the driver transistor coupled to the output of the delay circuit.
18. The integrated circuit of claim 12 , further comprising a fourth N-channel transistor and a fifth N-channel transistor coupled in series between the first power supply bus and the output of the delay circuit, control electrodes of the fourth and fifth N-channel transistors coupled to the output of the first inverter.