Mm-wave frequency peak detector

1. A peak detector circuit comprising:

a first switching device having a collector terminal, an emitter terminal, and a control terminal;

a second switching device having a collector terminal, an emitter terminal, and a control terminal;

a third switching device having a collector terminal, an emitter terminal, and a control terminal;

a fourth switching device having a collector terminal, an emitter terminal, and a control terminal;

a first load having a first terminal and a second terminal, said first terminal of said first load being connected to a ground;

a second load having a first terminal and a second terminal, said first terminal of said second load being connected to a ground;

a third load having a first terminal and a second terminal, said first terminal of said third load being connected to a supply voltage node;

a fourth load having a first terminal and a second terminal, said first terminal of said fourth load being connected to said supply voltage node;

a first output coupled to said second terminal of said first load and coupled to both of said emitter terminals of said first and second switching devices;

a second output coupled to said second terminal of said second load and coupled to both of said emitter terminals of said third and fourth switching devices;

a third output coupled to said second terminal of said third load and coupled to both of said collector terminals of said first and second switching devices; and

a fourth output coupled to said second terminal of said fourth load, and coupled to both of said collector terminals of said third and fourth switching devices, where said control terminals of said first and second switching devices are arranged to receive a differential input voltage, whereby said control terminals of said first, second, third, and fourth switching devices are arranged to be biased with a common DC bias voltage, and whereby said first, second, third and fourth load are selected so that:

R 1= R 2=α f*R 3=α f*R 4, with

R1, R2, R3, R4 a resistance of said first, second, third and fourth load, respectively, and of a common-base current gain of said switching devices.

2. The peak detector circuit according to claim 1 , wherein a first pair of cascade transistors is arranged between said second terminal of said third load and said collector terminals of said first and second switching devices.

3. The peak detector circuit according to claim 1 , wherein a second pair of cascade transistors is arranged between said second terminal of said fourth load and said collectors terminals of said third and fourth switching devices.

4. The peak detector circuit according to claim 1 , wherein each of said firth, second, third, and fourth loads comprises a resistor and a capacitor, wherein said capacitor is arranged to bypass an AC signal and its harmonics to ground.

5. The peak detector circuit according to claim 1 , wherein each of said first, second, third and fourth output is coupled to said second terminal of each of said first, second, third and fourth load via a low pass filter.

6. The peak detector circuit according to claim 5 , wherein said low pass filter comprises a capacitor and a resistor.

7. The peak detector circuit according to claim 1 , wherein said first, second, third, and fourth switching devices comprise npn bipolar transistors.

8. The peak detector circuit according to claim 1 , wherein said first, second, third, and fourth switching devices comprise hetero-junction bipolar transistors.

9. The peak detector circuit according to claim 1 , wherein said first, second, third, and fourth switching devices comprise NMOS transistors.

10. The peak detector circuit according to claim 1 , wherein said first, second, third, and fourth switching devices comprise III-IV silicon devices, such as gallium arsenide (GaAs) devices.

11. The peak detector device comprising at least one peak detector circuit according to claim 1 , wherein said peak detector device comprises an interface bus, such as a serial peripheral bus or a parallel interface bus, arranged to measure voltages of said first, second, third and fourth outputs, and a signal processing block arranged to handle said measured voltages and calculate a sensor voltage Vsensor where:

V sensor=( v sig B−v ref B )−( v sig T−v ref T ),

where vsigB is a voltage of said first output, vrefB is a voltage of said second output, vrefT is a voltage of said third output, vsigT is a voltage of said fourth output.

12. The peak detector device according to claim 11 , wherein said peak detector device comprises a plurality of peak detector circuits, wherein said interface bus is arranged to sequentially or simultaneously measure voltages of said outputs of said plurality of peak detector circuits and wherein said signal processing block is arranged to process said measured voltages and calculate an average detector voltage Vdetector_av where:

V detector_ av =(( v sig B 1− v ref B 1)−( v sig T 1− v ref T 1)+ . . . +( v sig Bn−v ref Bn )−( v sig Tn−v ref Tn ))/ N

where vsigBn is a voltage of said first output of a n-th circuit, vrefBn is a voltage of said second output of a n-th circuit, vrefTn is a voltage of said third output of a n-th circuit, vsigTn is a voltage of said fourth output of a n-th circuit, with n=1, . . . , N, with N being an integer value larger than 1.

13. A transmitter device comprising the peak detector circuit according to claim 1 .

14. The transmitter device according to claim 13 , wherein the transmitter device is a millimeter wave (mm Wave) transmitter.

15. A receiver device comprising the peak detector circuit according to claim 1 .

16. The receiver device according to claim 15 , wherein the receiver device is a millimeter wave (mm Wave) receiver.

17. A transceiver device comprising the peak detector circuit according to claim 1 .

18. The transceiver device according to claim 17 , wherein the transceiver device is a millimeter wave (mm Wave) transceiver.