APPARATUS AND METHOD FOR EXTERNAL ACCESS TO CORE RESOURCES OF A PROCESSOR, SEMICONDUCTOR SYSTEMS DEVELOPMENT TOOL COMPRISING THE APPARATUS, AND COMPUTER PROGRAM PRODUCT AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM ASSOCIATED WITH THE METHOD
There is disclosed an apparatus for external access to core resources ( 211,212 ) of a processor ( 2 ) comprising a processing core ( 21 ), a shared memory ( 22 ), and a multiple paths Direct Memory Access, DMA, controller ( 23 ). Access to core critical resources can be performed while the core is executing an application program. The proposed apparatus comprises a Manager module ( 13 ) which is operable to setup the DMA controller to copy the assigned core resources via allocated DMA channel into a safe memory region. Further, an Observer module ( 14 ) is operable to read the transferred data and make the correlation on the host apparatus side. This allows accessing data used by the core via the DMA controller into, e.g., a run-time debugger accessible region.
1 . An apparatus external access to core resources of a processor comprising a processing core, a shared memory, and a multiple paths Direct Memory Access, DMA, controller operable to transfer data between the processing core and the shared memory, the device comprising:
a User Interface configured to receive user requests with respect to data stored in the core resources of the processor;
a Manager module operable to configure the DMA controller with parameters to start the transfer of data from the core resources to the shared memory of the processor, responsive to a user request received through the User Interface;
an Observer module operable to read the data from the shared memory of the processor, responsive to an indication by the Manager module that the data transfer is completed; and
a Controller module configured to control operation of the User Interface, the Manager module and the Observer module while the processor is running in execution mode.
2 . The apparatus of claim 1 , wherein the core resources comprise at least one of an internal core memory and Memory Mapped Registers.
3 . The apparatus of claim 1 , wherein the Observer module is configured to correlate the read data and the user request, and to pass the read data to the Controller module.
4 . The apparatus of claim 3 , wherein the Controller module is further configured to return the read data to a user through the User Interface.
5 . The device of claim 3 , wherein the Controller module is further configured to process the read data and to return a feedback to a user through the User Interface based on the processed data.
6 . The apparatus of claim 5 , wherein the Controller module is a debugger program configured to process the read data according to a debugging scheme without interfering with the processor core execution of an application program under debug.
7 . The apparatus of claim 1 , wherein at least one of the Manager module and the Observer module is a software component.
8 . The apparatus of claim 1 , wherein the Controller module is further configured to upload data into the core resources by controlling the Observer module and the Manager module to perform a write operation through the shared memory and the DMA controller.
9 . A semiconductor systems development tool comprising an apparatus for external access to core resources of a processor according to claim 1 .
10 . A method of external access to core resources of a processor comprising a processing core, a shared memory, and a multiple paths Direct Memory Access, DMA, controller operable to transfer data between the processing core and the shared memory, the method comprising, while the processor is running in execution mode:
receiving a user request with respect to data stored in the core resources of the processor;
configuring the DMA controller with parameters to start the transfer of data from the core resources to the shared memory of the processor, responsive to the user request;
reading the data from the shared memory of the processor, responsive to an indication that the data transfer is completed.
11 . The method of claim 10 , further comprising correlating the read data and the user request.
12 . The method of claim 10 , further comprising returning the read data to a user.
13 . The method of claim 10 , further comprising processing the read data and returning a feedback to a user through the User Interface based on the processed data.
14 . The method of claim 13 , further comprising processing the read data according to a debugging scheme without interfering with the processor core execution of an application program under debug.
15 . A computer program product comprising one or more stored sequences of instructions that are accessible to a processor and which, when executed by the processor, cause the processor to carry out the steps of claim 10 .
16 . A non-transitory computer-readable storage medium, with computer-readable instructions stored therein for execution by a processor to perform the method of claim 10 .