IP Library Granted Patent US 9,985,684
Granted Patent B2
US 9,985,684 · App. 15/053,036 · Granted May 29, 2018

Passive equalizer capable of use in high-speed data communication

Inventor: Kevin Yi Cheng Chang (Austin, TX)
Assignee: NXP USA, INC.
H04B3/14H04B3/04H04B3/145
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Quick Facts
Patent No.
US 9,985,684
App. No.
15/053,036
Granted
May 29, 2018
Kind
B2
Abstract

A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.

Claims (56)

1. A passive equalizer comprising:

a first resistive element coupled between an input node and an output node;

a first inductive element and a second resistive element coupled in series between the output node and a first voltage supply node;

a first variable capacitor coupled between the input node and a first node located between the first inductive element and the second resistive element;

a second inductive element and a third resistive element coupled in series between the input node and a second voltage supply node, the first voltage supply node configured to supply a first voltage different from a second voltage supplied at the second voltage supply node; and

a first capacitive element coupled between the output node and a second node located between the second inductive element and the third resistive element.

2. The passive equalizer of claim 1 , wherein a first terminal of the second inductive element is coupled to the input node, a second terminal of the second inductive element is coupled to a first terminal of the third resistive element, and a second terminal of the third resistive element is coupled to the second voltage supply node.

3. The passive equalizer of claim 1 , wherein the first voltage supply node supplies a reference voltage and the second voltage supply node supplies a ground voltage.

4. The passive equalizer of claim 1 , further comprising:

an active equalizer, an input of the active equalizer coupled to the output node.

5. The passive equalizer of claim 1 , further comprising:

an active equalizer stage, an output of the active equalizer coupled to the input node.

6. The passive equalizer of claim 1 , wherein a first terminal of the first inductive element is coupled to the output node, a second terminal of the first inductive element is coupled to a first terminal of the second resistive element, and a second terminal of the second resistive element is coupled to the first voltage supply node.

7. The passive equalizer of claim 6 , wherein the first voltage supply node supplies a reference voltage.

8. The passive equalizer of claim 6 , wherein the second resistive element is a variable resistor.

9. The passive equalizer of claim 8 , wherein the first voltage supply node is characterized as ground.

10. A passive equalizer comprising:

a first input node;

a first output node;

a first resistive element coupled between the first input node and the first output node;

a first inductive element having a first terminal coupled to the first output node;

a first variable capacitor having a first terminal coupled to the first input node and a second terminal coupled to a second terminal of the first inductive element;

a first variable resistor having a first terminal coupled to a second terminal of the first inductive element and to the second terminal of the first variable capacitor, and a second terminal coupled to a first voltage supply node

a second resistive element coupled between a second input node and a second output node;

a second inductive element having a first terminal coupled to the second output node;

a second variable capacitor having a first terminal coupled to the second input node and a second terminal coupled to a second terminal of the second inductive element; and

a second variable resistor having a first terminal coupled to a second terminal of the second inductive element and to the second terminal of the second variable capacitor, and a second terminal coupled to the first voltage supply node;

wherein the first input node is configured to receive a first signal and the second input node is configured to receive a second signal, the second signal being a complementary signal of the first signal.

11. The passive equalizer of claim 10 , further comprising:

an active equalizer, wherein a first input of the active equalizer is coupled to the first output node and a second input of the active equalizer is coupled to the second output node.

12. The passive equalizer of claim 10 , further comprising:

an active equalizer stage, wherein a first output of the active equalizer stage is coupled to the first input node and a second output of the active equalizer stage is coupled to the second input node.

13. The passive equalizer of claim 10 , further comprising:

a third inductive element having a first terminal coupled to the first input node;

a first capacitive element having a first terminal coupled to the first output node and a second terminal coupled to a second terminal of the third inductive element; and

a third resistive element having a first terminal coupled to a second terminal of the third inductive element and to the second terminal of the first capacitive element, and a second terminal coupled to the first voltage supply node.

14. The passive equalizer of claim 13 , wherein the first voltage supply node is characterized as a ground node.

15. A receiver, comprising:

an active equalizer; and

a passive equalizer coupled to the active equalizer, the passive equalizer including:

a first resistive element coupled between an input node and an output node;

a first inductive element having a first terminal coupled to the output node;

a first variable capacitor having a first terminal coupled to the input node and a second terminal coupled to a second terminal of the first inductive element;

a second resistive element having a first terminal coupled to a second terminal of the first inductive element and to the second terminal of the first variable capacitor, and a second terminal coupled to a first voltage supply node, the first voltage supply node configured to supply a reference voltage;

a second inductive element and a third resistive element coupled in series between the input node and a second voltage supply node, the second voltage supply node configured to supply a voltage different from the reference voltage; and

a first capacitive element coupled between the output node and a second node located between the second inductive element and the third resistive element.

16. The receiver of claim 15 , wherein an output of the active equalizer is coupled to the input node of the passive equalizer.

17. The receiver of claim 15 , wherein the first output node of the passive equalizer is coupled to an input of the active equalizer.

18. The receiver of claim 15 , wherein a first terminal of the first inductive element is coupled to the output node, a second terminal of the first inductive element is coupled to a first terminal of the second resistive element, and a second terminal of the second resistive element is coupled to the first voltage supply node.

19. The receiver of claim 15 , wherein a first terminal of the second inductive element is coupled to the input node, a second terminal of the second inductive element is coupled to a first terminal of the third resistive element, and a second terminal of the third resistive element is coupled to the second voltage supply node.

20. The receiver of claim 15 , further comprises:

a fourth resistive element coupled between a second input node and a second output node;

a third inductive element having a first terminal coupled to the second output node;

a second variable capacitor having a first terminal coupled to the second input node and a second terminal coupled to a second terminal of the third inductive element; and

a fifth resistive element having a first terminal coupled to a second terminal of the third inductive element and to the second terminal of the second variable capacitor, and a second terminal coupled to a third voltage supply node;

wherein the input node is configured to receive a first signal and the second input node is configured to receive a second signal, the second signal being a complementary signal of the first signal.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2016
From: CHANG, KEVIN YI CHENG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037826/0892 →
Continuity (1)
Related Publication 20170250730A1 · Aug 31, 2017