IP Library Granted Patent US 10,445,133
Granted Patent B2
US 10,445,133 · App. 15/060,692 · Granted Oct 15, 2019

Data processing system having dynamic thread control

Inventors: Jonathan J. Gamoneda (Austin, TX); Jehoda Refaeli (Austin, TX); Jeffrey W. Scott (Austin, TX)
Assignee: NXP USA, Inc.
G06F9/485G06F11/36
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Quick Facts
Patent No.
US 10,445,133
App. No.
15/060,692
Granted
Oct 15, 2019
Kind
B2
Abstract

A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.

Claims (41)

1. A method for managing thread execution in a processing system configured to execute at least two threads, the method comprising:

setting a first watchpoint and a second watchpoint, wherein the first watchpoint and the second watchpoint correspond to a first thread of the at least two threads;

after setting the first watchpoint and the second watchpoint, commencing execution of the at least two threads in accordance with a normal priority of each thread;

while executing the first thread, generating a first watchpoint trigger when the first watchpoint of the first thread is hit; and

in response to the first watchpoint trigger, controlling execution of each thread of the at least two threads in accordance with a value stored in a first control register corresponding to the first thread, wherein the value indicates a priority of each thread of the at least two threads by indicating a percentage of execution time of each thread of the at least two threads and the priority for each thread is different from the normal priority of each thread; and

while executing the first thread, after generating the first watchpoint trigger, generating a second watchpoint trigger when the second watchpoint of the first thread is hit; and

in response to the second watchpoint trigger, resuming the normal priority of each of the at least two threads.

2. The method of claim 1 , wherein controlling execution of the at least two threads further comprises disabling execution of the first thread and not disabling execution of the second thread, the disabling execution of the first thread occurring between the first watchpoint trigger and the second watchpoint trigger.

3. The method of claim 1 , further comprising setting a flag in the first control register, the flag providing an indication to a second thread that execution of one or more threads is affected by the first watchpoint trigger.

4. The method of claim 1 , wherein setting the first watchpoint further comprises setting the first watchpoint during execution of boot code.

5. The method of claim 1 , wherein the first watchpoint is triggered by an interrupt during execution of application code.

6. The method of claim 1 , wherein the first watchpoint includes a watchpoint start address and the second watchpoint includes a watchpoint end address.

7. The method of claim 6 , further comprising:

enabling a first watchpoint region corresponding to the first thread by setting the first watchpoint and the second watchpoint; and

using a debug unit for determining that code execution enters the first watchpoint region, and for generating the first watchpoint trigger corresponding to code execution entering the first watchpoint region.

8. The method of claim 7 , further comprising:

enabling a second watchpoint region corresponding to a second thread;

generating a third watchpoint trigger corresponding to code execution entering the second watchpoint region; and

in response to the third watchpoint trigger, controlling execution of the at least two threads in accordance with a value stored in a second control register corresponding to the second thread, wherein the value stored in the second control register indicates a priority of each thread of the at least two threads.

9. A method for managing thread execution in a processing system configured to execute at least two threads, the method comprising:

enabling a first watchpoint region corresponding to a first thread, the first watchpoint region beginning at a first watchpoint and ending at a second watchpoint, wherein execution of the at least two threads begins after enabling the first watchpoint and the second watchpoint and the at least two threads execute in accordance with a normal priority of each thread;

generating a first watchpoint trigger when a first address of executing code in the first thread matches the first watchpoint; and

in response to the first watchpoint trigger, controlling execution of each thread of the at least two threads based on a value stored in a first control register corresponding to the first thread, wherein the value indicates a priority of each thread of the at least two threads and the priority for each thread is different from the normal priority of each thread, and wherein controlling the execution of the at least two threads further comprises throttling execution of the first thread, the throttling execution of the first thread occurring within the watchpoint region; and

while executing the first thread, after generating the first watchpoint trigger, generating a second watchpoint trigger when a second address of executing code in the first thread matches the second watchpoint; and

in response to the second watchpoint trigger, resuming execution of the at least two threads in accordance with the normal priority of each thread.

10. The method of claim 9 , wherein controlling execution of the at least two threads further comprises disabling execution of the first thread, the disabling execution of the first thread occurring within the first watchpoint region.

11. The method of claim 9 , further comprising setting a flag in the first control register corresponding to the first thread, the flag providing an indication to the second thread that execution of one or more threads is affected by code execution in the first watchpoint region.

12. The method of claim 9 , wherein the first address of executing code matching the first watchpoint is a first program counter address of executing code matching the first watchpoint.

13. The method of claim 9 , wherein enabling the first watchpoint region further comprises enabling the first watchpoint region during execution of boot code.

14. A processing system, comprising:

a processor capable of executing code having two or more threads;

a memory coupled to the processor, the memory storing executable code;

a control unit coupled to the processor, the control unit commencing execution of the two or more threads in accordance with a normal priority of each thread;

the control unit further including a control register corresponding to each thread of the two or more threads, and in response to a watchpoint trigger occurring during execution of a first thread of the two or more threads and indicated by a first control register corresponding to the first thread, the control unit controls execution of each thread of the two or more threads based on a value stored in the first control register, wherein the value stored in the first control register indicates a priority of each thread of the two or more threads by indicating a percentage of execution time of each thread of the two or more threads and wherein the priority for each thread is different from the normal priority of each thread; and

a debug unit coupled to the control unit, the debug unit generating the watchpoint trigger based on code execution entering a first watchpoint region of the memory, wherein the first watchpoint region is indicated by the first control register corresponding to the first thread, wherein the debug unit further comprises generating a second watchpoint trigger corresponding to the first thread based on code execution exiting the first watchpoint region, and in response to the second watchpoint trigger, resuming execution of the two or more threads in accordance with the normal priority of each thread.

15. The processing system of claim 14 , wherein the control unit controlling the one or more threads further comprises disabling execution of the first thread, the disabling execution of the first thread occurring between the first watchpoint trigger and the second watchpoint trigger.

16. The method of claim 1 , wherein controlling execution of the at least two threads in accordance with the value stored in the first control register comprises executing the at least two threads in accordance with the priority indicated by the value stored in the first control register.

17. The method of claim 1 , wherein controlling execution of the at least two threads further comprises throttling execution of each of the at least two threads between the first watchpoint trigger and the second watchpoint trigger.

18. The method of claim 9 , wherein the method further comprises:

prior to generating the first watchpoint trigger, executing the at least two threads in accordance with a normal priority of each thread; and

while executing code is within the first watchpoint region, executing the at least two threads in accordance with the priority indicated by the value stored in the first control register.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2016
From: GAMONEDA, JONATHAN J.; REFAELI, JEHODA; SCOTT, JEFFREY W.
To: FREESCALE SEMICONDUCTOR, INC.; FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037889/0787 →