Split gate device with doped region and method therefor

1. A method of forming a semiconductor device using a substrate, comprising:

forming a first isolation region in the substrate, a first select gate over the substrate, a second select gate over the substrate spaced from the first select gate, a charge storage layer over the substrate including over the first and second select gates, and a control gate layer over the charge storage layer whereby the control gate layer has a top surface further from a top surface of the substrate (1) in a first region over and laterally adjacent to the first select gate and (2) in a second region over and laterally adjacent to the second select gate than in a third region between the first and second select gates, and wherein the control gate layer is continuous between the first and second select gates directly over the third region;

performing a first implant through the control gate layer with a strength sufficient to reach the substrate in the third region to form a doped region in the substrate and not sufficient to reach the substrate in the first and second regions; and

after performing the first implant, removing the control gate layer over a first portion of the doped region between the first select gate and the second select gate to leave a first control gate over the substrate adjacent to the first select gate and over a second portion of the doped region to leave a second control gate over the substrate adjacent to the second select gate and over a third portion of the doped region.

2. The method of claim 1 comprising:

forming an insulating layer over the control gate layer;

wherein:

the performing the first implant is performed after forming the insulating layer.

3. The method of claim 2 , further comprising removing the insulating layer over the first portion of the doped region prior to the removing of the control gate layer over the first portion of the doped region.

4. The method of claim 3 , wherein, prior to the removing the insulating layer over the first portion of the doped region, the insulating layer has a first sidewall between the first and second select gates and a second sidewall between the first and second select gates, the first sidewall is closer to the first select gate than the second select gate, and the second sidewall is closer to the second select gate than the first select gate, further comprising:

forming a first sidewall spacer on the first sidewall and a second sidewall spacer on the second sidewall, wherein the first and second sidewall spacers are formed prior to the performing the first implant.

5. The method of claim 1 , wherein the control gate layer has a first sidewall between the first and second select gates and a second sidewall between the first and second select gates, the first sidewall of the control gate layer is closer to the first select gate than the second select gate, and the second sidewall of the select gate layer is closer to the second select gate than the first select gate, further comprising:

forming a first sidewall spacer on the first sidewall of the control gate layer and a second sidewall spacer on the second sidewall of the control gate layer, wherein the first and second sidewall spacers are formed prior to the performing the first implant.

6. The method of claim 1 further comprising:

forming an insulating layer over the control gate layer, wherein the first implant is performed prior to forming the insulating layer; and

after forming the insulating layer, performing a second implant through the control gate layer to form a second doped region in the substrate.

7. The method of claim 6 , wherein the second doped region in the substrate overlaps the doped region but is narrower than the doped region.

8. The method of claim 1 , further comprising forming a first anti-reflective coating over the first select gate and second anti-reflective coating over the second select gate prior to forming the charge storage layer.

9. The method of claim 1 , wherein after the removing the control gate layer over the first portion of the doped region to leave the first control gate and over the second portion of the doped region to leave a second control gate, the doped region extends under at least a portion of the first control gate and under at least a portion of the second control gate.

10. A method of forming a semiconductor device using a substrate, comprising:

forming a first select gate over the substrate;

forming a second select gate, spaced from the first select gate, over the substrate;

forming a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal;

forming a control gate layer over the charge storage layer, wherein the control gate layer is conformal;

performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate directly under the control gate layer in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

11. The method of claim 10 further comprising forming a first insulating layer over the control gate layer.

12. The method of claim 11 , wherein the performing the first implant occurs after forming the first insulating layer.

13. The method of claim 11 , wherein the performing the first implant occurs before forming the first insulating layer.

14. The method of claim 13 , further comprising performing a second implant after forming the first insulating layer.

15. The method of claim 11 wherein the insulating layer has a first sidewall and a second sidewall between the first select gate and the second select gate, further comprising:

forming a first sidewall spacer on the first sidewall; and

forming a second sidewall spacer on the second sidewall;

wherein the performing the first implant occurs after the forming the first sidewall spacer and the forming the second sidewall spacer.

16. The method of claim 10 , wherein the control gate layer has a first sidewall and a second sidewall between the first select gate and the second select gate, further comprising:

forming a first sidewall spacer on the first sidewall;

forming a second sidewall spacer on the second sidewall;

wherein the performing the first implant occurs after the forming the first sidewall spacer and the forming the second sidewall spacer.

17. The method of claim 10 further comprising:

forming a first insulating layer over the control gate layer, wherein the first insulating layer is conformal; and

performing a second implant through the first insulating later and into a second portion of the region between the first select gate and the second select gate that is within the first portion and less than the first portion.

18. The method of claim 10 , wherein the charge storage layer comprises nanocrystals.

19. The method of claim 10 , further comprising:

after performing the first implant, removing the control gate layer over a first portion of the doped region between the first select gate and the second select gate to leave a first control gate over the substrate adjacent to the first select gate and over a second portion of the doped region to leave a second control gate over the substrate adjacent to the second select gate and over a third portion of the doped region.

20. The method of claim 19 , wherein after the removing the control gate layer over the first portion of the doped region to leave the first control gate and over the second portion of the doped region to leave a second control gate, the doped region extends under at least a portion of the first control gate and under at least a portion of the second control gate.