Method and apparatus for validating a test pattern
A method and apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, IC, design. The method comprises calculating at least one weighted rise activity, WRA, value for at least one region of the IC design based at least partly on rising gate transitions within the at least one region of the IC design when the test pattern is applied thereto, calculating at least one weighted fall activity, WFA, value for the at least one region of the IC design based at least partly on fall gate transitions within the at least one region of the IC design when the test pattern is applied thereto, and validating the test pattern based at least partly on the WRA value and the WFA value.
1. A method performed by an electronic design automation apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, IC, design, the method comprising:
calculating by the electronic design automation apparatus, at least one weighted rise activity, WRA, value for at least one region of the IC design based at least partly on rising gate transitions within the at least one region of the IC design when the test pattern is applied thereto;
calculating by the electronic design automation apparatus, at least one weighted fall activity, WFA, value for the at least one region of the IC design based at least partly on fall gate transitions within the at least one region of the IC design when the test pattern is applied thereto; and
validating by the electronic design automation apparatus, the test pattern based at least partly on the WRA value and the WFA value, wherein the validating the test pattern is based at least partly on a comparison of the calculated WRA value with a WRA threshold value and a comparison of the calculated WFA value with a WFA threshold value for the at least one region.
2. The method of claim 1 , wherein the method comprises:
determining the WRA threshold value for the at least one region of the IC design;
determining the WFA threshold value for the at least one region of the IC design; and.
3. The method of claim 1 , wherein the method comprises dividing the IC design into a plurality of regions and for each region:
calculating at least one WRA value;
calculating at least one WFA value; and
validating the test pattern for the respective region based at least partly on the WRA value and the WFA value.
4. The method of claim 2 , wherein the WRA threshold value for the at least one region of the IC design is determined based at least partly on at least one parameter from a group comprising:
a charge supply capacity of a high voltage power distribution network for the at least one region of the IC design;
a functional component of the IC design to which the at least one region of the IC design relates;
a type of IC package; and
a process corner.
5. The method of claim 2 , wherein the WFA threshold value for the at least one region of the IC design is determined based at least partly on at least one parameter from a group comprising:
a charge sink capacity of a low voltage power distribution network for the at least one region of the IC design;
a functional component of the IC design to which the at least one region of the IC design relates;
a type of IC package; and
a process corner.
6. The method of claim 1 , wherein the method comprises dividing the IC design into a plurality of regions comprising at least one of:
power domain regions;
functional regions; and
grid based regions.
7. The method of claim 1 , wherein calculating a WRA value for the at least one region of the IC design comprises identifying all gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto and calculating the WRA value for the at least one region of the IC design based at least partly on the identification of gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto.
8. The method of claim 6 , wherein calculating a WRA value for the at least one region of the IC design comprises:
identifying all gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto;
determining a weighted value for each identified gate based on a fan-out count for the respective gate; and
summing the weighted gate values of the identified gates to obtain the WRA value for the at least one region of the IC design.
9. The method of claim 1 , wherein calculating a WFA value for the at least one region of the IC design comprises identifying all gates in the at least one region that are caused to transition from a high logical state to a low logical state when the test pattern is applied thereto and calculating the WFA value for the at least one region of the IC design based at least partly on the identification of gates in the at least one region that are caused to transition from a high logical state to a low logical state when the test pattern is applied thereto.
10. The method of claim 8 , wherein calculating a WFA value for the at least one region of the IC design comprises:
identifying all gates in the at least one region that are caused to transition from a high logical state to a low logical state when the test pattern is applied thereto;
determining a weighted value for each identified gate based on a fan-out count for the respective gate; and
summing the weighted gate values of the identified gates to obtain the WFA value for the at least one region of the IC design.
11. A method performed by an electronic design automation apparatus of automated test pattern generation for generating test patterns used during at-speed testing, the method comprising:
generating a set of test patterns comprising at least one test pattern for at-speed testing of at least one integrated circuit, IC, design;
validating the at least one at-speed test pattern of the set of test patterns using the method of claim 1 ; and
outputting a subset of validated test patterns.
12. The method of claim 2 , wherein the method comprises dividing the IC design into a plurality of regions and for each region:
calculating at least one WRA value;
calculating at least one WFA value; and
validating the test pattern for the respective region based at least partly on the WRA value and the WFA value.
13. The method of claim 3 , wherein the WRA threshold value for the at least one region of the IC design is determined based at least partly on at least one parameter from a group comprising:
a charge supply capacity of a high voltage power distribution network for the at least one region of the IC design;
a functional component of the IC design to which the at least one region of the IC design relates;
a type of IC package; and
a process corner.
14. The method of claim 3 , wherein the WFA threshold value for the at least one region of the IC design is determined based at least partly on at least one parameter from a group comprising:
a charge sink capacity of a low voltage power distribution network for the at least one region of the IC design;
a functional component of the IC design to which the at least one region of the IC design relates;
a type of IC package; and
a process corner.
15. The method of claim 4 , wherein the WFA threshold value for the at least one region of the IC design is determined based at least partly on at least one parameter from a group comprising:
a charge sink capacity of a low voltage power distribution network for the at least one region of the IC design;
a functional component of the IC design to which the at least one region of the IC design relates;
a type of IC package; and
a process corner.
16. The method of claim 2 , wherein calculating a WRA value for the at least one region of the IC design comprises identifying all gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto and calculating the WRA value for the at least one region of the IC design based at least partly on the identification of gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto.
17. The method of claim 3 , wherein calculating a WRA value for the at least one region of the IC design comprises identifying all gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto and calculating the WRA value for the at least one region of the IC design based at least partly on the identification of gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto.
18. The method of claim 4 , wherein calculating a WRA value for the at least one region of the IC design comprises identifying all gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto and calculating the WRA value for the at least one region of the IC design based at least partly on the identification of gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto.
19. The method of claim 5 , wherein calculating a WRA value for the at least one region of the IC design comprises identifying all gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto and calculating the WRA value for the at least one region of the IC design based at least partly on the identification of gates in the at least one region that are caused to transition from a low logical state to a high logical state when the test pattern is applied thereto.