Semiconductor device and method of forming an embedded SoP fan-out package
A semiconductor device includes a BGA package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.
1. A method of making a semiconductor device, comprising:
providing a semiconductor package including a first semiconductor die and a first encapsulant disposed over the first semiconductor die;
disposing a second semiconductor die over the semiconductor package;
forming a plurality of bumps over the semiconductor package and around the second semiconductor die;
depositing a second encapsulant in contact with the semiconductor package and around the second semiconductor die and in contact with the bumps, wherein a portion of the bumps extends outward beyond the second encapsulant and an active surface of the second semiconductor die is coplanar with a surface of the second encapsulant; and
forming an interconnect structure over the second semiconductor die and second encapsulant and contacting the bumps after depositing the second encapsulant.
2. The method of claim 1 , further including removing a portion of the second encapsulant.
3. The method of claim 1 , further including removing a portion of the first encapsulant.
4. The method of claim 1 , further including disposing a supporting layer over the second encapsulant.
5. The method of claim 1 , wherein a width of the semiconductor package is substantially equal to a width of the semiconductor device.
6. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
depositing a first encapsulant over the first semiconductor die;
disposing a second semiconductor die over the first semiconductor die;
forming a vertical interconnect structure around the second semiconductor die;
depositing a second encapsulant in contact with the first encapsulant and around the second semiconductor die and in contact with the vertical interconnect structure, wherein an active surface of the second semiconductor die substantially resides at a surface of the second encapsulant; and
forming an interconnect structure over the second semiconductor die and second encapsulant and contacting the vertical interconnect structure after depositing the second encapsulant.
7. The method of claim 6 , wherein the vertical interconnect structure includes a plurality of bumps.
8. The method of claim 6 , further including removing a portion of the second encapsulant.
9. The method of claim 6 , further including removing a portion of the first encapsulant.
10. The method of claim 6 , further including disposing a supporting layer over the second encapsulant.
11. The method of claim 6 , wherein a height of the vertical interconnect structure is greater than a height of the second semiconductor die.
12. A method of making a semiconductor device, comprising:
providing a semiconductor package;
disposing a first semiconductor die over the semiconductor package;
forming a vertical interconnect structure over the semiconductor package and around the first semiconductor die; and
depositing a first encapsulant around the semiconductor package and further around the first semiconductor die and in contact with the vertical interconnect structure, wherein a portion of the vertical interconnect structure extends beyond the first encapsulant and a surface of the first semiconductor die substantially resides at a surface of the first encapsulant.
13. The method of claim 12 , wherein providing the semiconductor package includes:
providing a second semiconductor die; and
disposing a second encapsulant over the second semiconductor die.
14. The method of claim 13 , further including removing a portion of the second encapsulant.
15. The method of claim 12 , further including forming an interconnect structure over the first semiconductor die and first encapsulant and contacting the vertical interconnect structure after depositing the first encapsulant.
16. The method of claim 12 , further including removing a portion of the first encapsulant.
17. The method of claim 12 , further including disposing a supporting layer over the first encapsulant.
18. A semiconductor device, comprising:
a semiconductor package;
a first semiconductor die disposed over the semiconductor package;
a vertical interconnect structure formed over the semiconductor package and around the first semiconductor die; and
a first encapsulant deposited around the semiconductor package and further around the first semiconductor die and in contact with the vertical interconnect structure, wherein a portion of the vertical interconnect structure extends beyond the first encapsulant and a surface of the first semiconductor die substantially resides at a surface of the first encapsulant.
19. The semiconductor device of claim 18 , wherein the semiconductor package includes:
a second semiconductor die; and
a second encapsulant disposed over the second semiconductor die.
20. The semiconductor device of claim 18 , further including an interconnect structure formed over the first semiconductor die and first encapsulant and electrically connected to the vertical interconnect structure.
21. The semiconductor device of claim 18 , further including an opening in the first encapsulant.
22. The semiconductor device of claim 18 , further including a supporting layer disposed over the first encapsulant.
23. The semiconductor device of claim 18 , wherein a width of the semiconductor package is substantially equal to a width of the semiconductor device.