Patent Assignment
Reel/Frame 051365/0680
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2019-12-18
Received: 2019-12-18
Pages: 22
Assignor
STATS CHIPPAC PTE. LTD.
Executed: 2019-11-28
Assignee
JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
NO. 500 LINJIANG ROAD, YUECHENG DISTRICT, SHAOXING, CNX, CHINA
Covered Applications
(100)
METHOD OF PACKAGING THIN DIE AND SEMICONDUCTOR DEVICE INCLUDING THIN DIE
App. No. 15/919,401
→
Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System In Package
App. No. 15/705,543
→
Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic Passivation
App. No. 15/675,556
→
Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages
App. No. 15/674,247
→
Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP)
App. No. 15/618,343
→
Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor Package
App. No. 15/594,443
→
Semiconductor Device and Method of Forming Interconnect Substrate for FO-WLCSP
App. No. 15/584,697
→
Semiconductor Device and Method of Making Wafer Level Chip Scale Package
App. No. 15/582,418
→
Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
App. No. 15/473,447
→
Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect
App. No. 15/473,470
→
Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package
App. No. 15/457,736
→
Semiconductor Device and Method of Using Substrate Having Base and Conductive Posts to Form Vertical Interconnect Structure in Embedded Die Package
App. No. 15/380,788
→
Semiconductor Device and Method of Singulating Thin Semiconductor Wafer on Carrier Along Modified Region Within Non-Active Region Formed by Irradiating Energy
App. No. 15/379,178
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMI SHIELDING LAYER WITH CONDUCTIVE MATERIAL AROUND SEMICONDUCTOR DIE
App. No. 15/280,632
→
Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier
App. No. 15/218,536
→
Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP
App. No. 15/218,847
→
Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring
App. No. 15/177,081
→
Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP
App. No. 15/169,261
→
Semiconductor Device and Method of Forming an Embedded SOP Fan-Out Package
App. No. 15/167,830
→
Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor Package
App. No. 15/130,452
→
Semiconductor Device and Method of Forming a Package In-Fan Out Package
App. No. 15/082,190
→
Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive Channels
App. No. 15/069,719
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SACRIFICIAL ADHESIVE OVER CONTACT PADS OF SEMICONDUCTOR DIE
App. No. 15/068,290
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A LOW PROFILE EMBEDDED WAFER LEVEL BALL GRID ARRAY MOLDED LASER PACKAGE (EWLB-MLP)
App. No. 15/007,518
→
Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region
App. No. 14/974,002
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME OVER SEMICONDUCTOR DIE TO PROVIDE VERTICAL INTERCONNECT
App. No. 14/971,291
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDER BUMP METALLIZATION AND METHOD OF MANUFACTURE THEREOF
App. No. 14/955,033
→
Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package
App. No. 14/814,906
→
INTEGRATED CIRCUIT SYSTEM WITH DEBONDING ADHESIVE AND METHOD OF MANUFACTURE THEREOF
App. No. 14/791,287
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLP WITH SEMICONDUCTOR DIE EMBEDDED WITHIN PENETRABLE ENCAPSULANT BETWEEN TSV INTERPOSERS
App. No. 14/710,393
→
Semiconductor Device and Method of Mounting Semiconductor Die to Heat Spreader on Temporary Carrier and Forming Polymer Layer and Conductive Layer Over the Die
App. No. 14/697,950
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
App. No. 14/697,352
→
Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
App. No. 14/694,811
→
Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP)
App. No. 14/627,347
→
Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die
App. No. 14/612,075
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS THROUGH INTERCONNECT STRUCTURES AND ENCAPSULANT OF WLCSP
App. No. 14/566,870
→
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
App. No. 14/564,427
→
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
App. No. 14/563,448
→
Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
App. No. 14/553,358
→
Semiconductor Device and Method of Forming Wire Bondable Fan-Out EWLB Package
App. No. 14/548,064
→
Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation
App. No. 14/512,614
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE OVER SEED LAYER ON CONTACT PAD OF SEMICONDUCTOR DIE WITHOUT UNDERCUTTING SEED LAYER BENEATH INTERCONNECT STRUCTURE
App. No. 14/503,698
→
SEMICONDUCTOR DEVICE AND METHOD OF USING LEADFRAME BODIES TO FORM OPENINGS THROUGH ENCAPSULANT FOR VERTICAL INTERCONNECT OF SEMICONDUCTOR DIE
App. No. 14/466,923
→
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
App. No. 14/462,347
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING WAFER LEVEL CHIP SCALE PACKAGE
App. No. 14/449,914
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL TO SECURE SEMICONDUCTOR DIE TO CARRIER IN WLCSP
App. No. 14/340,187
→
Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer
App. No. 14/331,050
→
Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer
App. No. 14/328,922
→
Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier
App. No. 14/326,237
→
Semiconductor Device and Method of Forming Conductive Vias by Backside Via Reveal with CMP
App. No. 14/316,561
→
Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic Passivation
App. No. 14/316,225
→
Semiconductor Device Including RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
App. No. 14/292,925
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE LAYER OVER INSULATING LAYER FOR BONDING CARRIER TO MIXED SURFACES OF SEMICONDUCTOR DIE AND ENCAPSULANT
App. No. 14/288,643
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER
App. No. 14/288,589
→
Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
App. No. 14/289,344
→
Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die
App. No. 14/284,752
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
App. No. 14/274,599
→
Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
App. No. 14/267,800
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING BUMPS FORMED ON SEMICONDUCTOR DIE INTO PENETRABLE ADHESIVE LAYER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
App. No. 14/265,782
→
Semiconductor Device and Method of Stacking Semiconductor Die on a Fan-Out WLCSP
App. No. 14/261,252
→
Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
App. No. 14/257,850
→
Semiconductor Device and Method of Forming RDL and Vertical Interconnect by Laser Direct Structuring
App. No. 14/228,531
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS USING BACKSIDE VIA REVEAL AND SELECTIVE PASSIVATION
App. No. 14/222,547
→
Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor Package
App. No. 14/220,336
→
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
App. No. 14/194,691
→
Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package
App. No. 14/187,014
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDER BUMP METALLIZATION AND METHOD OF MANUFACTURE THEREOF
App. No. 14/140,829
→
Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages
App. No. 14/139,312
→
SEMICONDUCTOR DEVICE AND METHOD OF WAFER THINNING INVOLVING EDGE TRIMMING AND CMP
App. No. 14/134,907
→
Semiconductor Device and Method of Reducing Warpage Using a Silicon to Encapsulant Ratio
App. No. 14/109,313
→
SEMICONDUCTOR DEVICE INCLUDING INTEGRATED PASSIVE DEVICE FORMED OVER SEMICONDUCTOR DIE WITH CONDUCTIVE BRIDGE AND FAN-OUT REDISTRIBUTION LAYER
App. No. 14/092,304
→
Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants
App. No. 14/080,609
→
Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP
App. No. 14/079,273
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP
App. No. 14/043,751
→
INTEGRATED CIRCUIT THROUGH-SUBSTRATE VIA SYSTEM WITH A BUFFER LAYER AND METHOD OF MANUFACTURE THEREOF
App. No. 14/040,413
→
INTEGRATED CIRCUIT SYSTEM WITH DEBONDING ADHESIVE AND METHOD OF MANUFACTURE THEREOF
App. No. 14/038,275
→
Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor Package
App. No. 14/035,726
→
Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure
App. No. 14/021,056
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY ADJACENT TO SENSITIVE REGION OF SEMICONDUCTOR DIE USING WAFER-LEVEL UNDERFILL MATERIAL
App. No. 14/021,206
→
SEMICONDUCTOR DEVICE HAVING BALANCED BAND-PASS FILTER IMPLEMENTED WITH LC RESONATORS
App. No. 14/018,282
→
Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
App. No. 14/017,963
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/966,259
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH MOLD HOLE WITH ALIGNMENT AND DIMENSION CONTROL
App. No. 13/950,122
→
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
App. No. 13/943,735
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPEN CAVITY IN TSV INTERPOSER TO CONTAIN SEMICONDUCTOR DIE IN WLCSMP
App. No. 13/943,737
→
Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer
App. No. 13/939,044
→
Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure
App. No. 13/937,952
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PENETRABLE FILM ENCAPSULANT AROUND SEMICONDUCTOR DIE AND INTERCONNECT STRUCTURE
App. No. 13/937,849
→
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
App. No. 13/935,963
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV SEMICONDUCTOR WAFER WITH EMBEDDED SEMICONDUCTOR DIE
App. No. 13/936,099
→
Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier
App. No. 13/933,406
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING AN EMBEDDED WAFER LEVEL BALL GRID ARRAY (EWLB) PACKAGE ON PACKAGE (POP) DEVICE WITH A SLOTTED METAL CARRIER INTERPOSER
App. No. 13/918,103
→
Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP
App. No. 13/887,180
→
PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
App. No. 13/845,409
→
Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP
App. No. 13/845,542
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure
App. No. 13/845,329
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/844,160
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/842,582
→
Semiconductor Device having Wire Studs as Vertical Interconnect in FO-WLP
App. No. 13/832,781
→
SEMICONDUCTOR DEVICE AND METHOD OF USING PARTIAL WAFER SINGULATION FOR IMPROVED WAFER LEVEL EMBEDDED SYSTEM IN PACKAGE
App. No. 13/801,675
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