IP Library Granted Patent US 10,068,862
Granted Patent B2
US 10,068,862 · App. 15/082,190 · Granted Sep 4, 2018

Semiconductor device and method of forming a package in-fan out package

Inventors: Byung Tai Do (Singapore, SG); Arnel Senosa Trasporto (Singapore, SG)
Assignee: STATS ChipPAC Pte. Ltd.
H01L24/11H01L21/561H01L23/49811H01L24/19H01L24/20H01L25/03H01L25/105H01L25/50H01L23/3128H01L23/5383H01L23/5389H01L24/81H01L24/83H01L24/97H01L2224/0401H01L2224/04105H01L2224/12105H01L2224/16113H01L2224/16227H01L2224/2919H01L2224/32225H01L2224/73267H01L2224/81191H01L2224/81815H01L2224/83005H01L2224/83192H01L2224/92244H01L2224/94H01L2224/97H01L2225/1035H01L2225/1058H01L2924/15311H01L2924/19105H01L2924/19106
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Quick Facts
Patent No.
US 10,068,862
App. No.
15/082,190
Granted
Sep 4, 2018
Kind
B2
Abstract

A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package. The first semiconductor package includes an interposer and a second semiconductor die disposed over the interposer. A second encapsulant is deposited over the interposer and second semiconductor die. A first semiconductor die is disposed over the surface of the first semiconductor package. A second interconnect structure extends from the first semiconductor die opposite the first semiconductor package. A first encapsulant is deposited over the first semiconductor package and first semiconductor die. A portion of the first encapsulant over the first interconnect structure and second interconnect structure is removed. A discrete component is disposed on the surface of the first semiconductor package. A build-up interconnect structure is formed over the first semiconductor package and first semiconductor die. The first semiconductor package includes a molded laser package.

Claims (54)

1. A method of making a semiconductor device, comprising:

providing a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package;

disposing a first semiconductor die over the surface of the first semiconductor package within a height of the first interconnect structure and including a second interconnect structure extending over the first semiconductor die opposite the first semiconductor package;

depositing a first encapsulant over the first semiconductor package and first semiconductor die; and

planarizing the first encapsulant to expose the first interconnect structure and second interconnect structure.

2. The method of claim 1 , further including disposing a discrete component on the surface of the first semiconductor package.

3. The method of claim 1 , wherein providing the first semiconductor package includes:

providing an interposer;

disposing a second semiconductor die over the interposer;

depositing a second encapsulant over the interposer and second semiconductor die; and

disposing the first interconnect structure over the interposer opposite the second semiconductor die.

4. The method of claim 3 , further including:

disposing a solder bump over the interposer; and

removing a portion of the second encapsulant by laser direct ablation (LDA) to expose the solder bump.

5. The method of claim 1 , further including forming a build-up interconnect structure over the first semiconductor package and first semiconductor die, wherein a conductive layer of the build-up interconnect structure physically contacts the first interconnect structure and second interconnect structure.

6. The method of claim 1 , further including:

providing a second semiconductor package including the first semiconductor die; and

disposing the second semiconductor package over the surface of the first semiconductor package.

7. A method of making a semiconductor device, comprising:

providing a first semiconductor package including a first interconnect structure;

providing a first semiconductor die including a second interconnect structure extending over an active surface of the first semiconductor die;

disposing the first semiconductor die over the first semiconductor package with the active surface of the first semiconductor die oriented away from the first semiconductor package;

depositing a first encapsulant over the first semiconductor package and first semiconductor die; and

forming a third interconnect structure over the first semiconductor package, first semiconductor die, and first encapsulant.

8. The method of claim 7 , further including disposing a second semiconductor package over the first semiconductor package opposite the first semiconductor die.

9. The method of claim 7 , wherein the first interconnect structure includes a conductive bump or conductive pillar.

10. The method of claim 7 , wherein the second interconnect structure includes a conductive bump or conductive pillar.

11. The method of claim 7 , further including forming a build-up interconnect structure over the first semiconductor package and first semiconductor die.

12. The method of claim 7 , further including disposing a discrete component over the first semiconductor package adjacent to the first semiconductor die.

13. The method of claim 7 , wherein providing the first semiconductor package further includes:

providing an interposer;

disposing a second semiconductor die over the interposer; and

depositing a second encapsulant over the second semiconductor die and the interposer.

14. A method of making a semiconductor device, comprising:

providing a first semiconductor package including a first interconnect structure disposed over a surface of the first semiconductor package; and

disposing a first semiconductor die over the surface of the first semiconductor package including a second interconnect structure of the first semiconductor die oriented away from the first semiconductor package.

15. The method of claim 14 , further including disposing a discrete component over the surface of the first semiconductor package.

16. The method of claim 14 , further including providing the first semiconductor package to include an interposer.

17. The method of claim 14 , further including disposing a second semiconductor package over the first semiconductor package opposite the first semiconductor die.

18. The method of claim 17 , further including providing the first semiconductor package as a molded laser package.

19. The method of claim 14 , further including forming a fan-out interconnect structure over the first semiconductor package and first semiconductor die.

20. A method of making a semiconductor device, comprising:

providing a first semiconductor package;

disposing a first semiconductor die over the first semiconductor package with an active surface of the first semiconductor die oriented away from the first semiconductor package; and

forming an interconnect structure over the first semiconductor package and first semiconductor die to electrically couple the first semiconductor package to the first semiconductor die.

21. The method of claim 20 , further including depositing an encapsulant over the first semiconductor package and first semiconductor die.

22. The method of claim 21 , further including:

disposing a first conductive pillar on the first semiconductor package; and

removing a portion of the encapsulant over the first conductive pillar.

23. The method of claim 22 , further including:

disposing a second conductive pillar on the first semiconductor die; and

removing a portion of the encapsulant over the second conductive pillar.

24. The method of claim 20 , further including disposing a molded laser package over the interconnect structure.

25. The method of claim 20 , further including disposing a discrete component over the first semiconductor package.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2016
From: DO, BYUNG TAI; TRASPORTO, ARNEL SENOSA
To: STATS CHIPPAC, LTD.
Reel/Frame 038111/0838 →
Continuity (2)
Provisional Application 62145084 · Apr 9, 2015
Related Publication 20160300817A1 · Oct 13, 2016
Cited By (1)
US 12,525,587