Semiconductor device and method of making wafer level chip scale package
A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.
1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer;
forming a redistribution layer including an interconnect site over the semiconductor wafer;
forming a first insulating layer extending over the semiconductor wafer and in contact with the redistribution layer with an opening extending between opposing side surfaces of the first insulating layer over the interconnect site with no portion of the first insulating layer within the opening; and
forming an interconnect structure partially within the opening to cover a top surface of the redistribution layer and a side surface of the redistribution layer, wherein a portion of the interconnect structure extends above the first insulating layer and a width of the opening is greater than a width of the interconnect structure with no contact between the interconnect structure and the first insulating layer.
2. The method of claim 1 , further including:
forming a second insulating layer over the semiconductor wafer; and
forming the redistribution layer over the second insulating layer.
3. The method of claim 2 , wherein the opening extends to the second insulating layer.
4. The method of claim 1 , further including forming the opening partially through the first insulating layer.
5. The method of claim 1 , further including forming a conductive layer over the semiconductor wafer, wherein the redistribution layer contacts the conductive layer.
6. The method of claim 1 , further including:
singulating the semiconductor wafer into individual semiconductor die; and
disposing the semiconductor die over a substrate.
7. A semiconductor device, comprising:
a semiconductor wafer;
a redistribution layer including an interconnect site formed over the semiconductor wafer;
a first insulating layer formed over the redistribution layer with an opening in the first insulating layer over the interconnect site with no portion of the first insulating layer within the opening; and
an interconnect structure designated for external interconnect of the semiconductor device formed within the opening to cover a top surface of the redistribution layer and a side surface of the redistribution layer, wherein a portion of the interconnect structure extends above the first insulating layer and a width of the opening is greater than a width of the interconnect structure with no contact between the interconnect structure and the first insulating layer.
8. The semiconductor device of claim 7 , further including a second insulating layer formed over the semiconductor wafer, wherein the redistribution layer is formed over the second insulating layer.
9. The semiconductor device of claim 8 , wherein the opening extends to the second insulating layer.
10. The semiconductor device of claim 7 , wherein the opening is formed partially through the first insulating layer.
11. The semiconductor device of claim 7 , further including a conductive layer formed over the semiconductor wafer, wherein the redistribution layer contacts the conductive layer.
12. The semiconductor device of claim 7 , wherein the interconnect structure includes a bump.