IP Library Granted Patent US 8,823,182
Granted Patent B2
US 8,823,182 · App. 13/935,963 · Granted Sep 2, 2014

Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant

Inventors: Linda Pei Ee Chua (Singapore, SG); Byung Tai Do (Singapore, SG); Reza A. Pagaila (Tangerang, ID)
Assignee: STATS ChipPAC, Ltd.
H01L23/48H01L23/552H01L23/52H01L29/40
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Quick Facts
Patent No.
US 8,823,182
App. No.
13/935,963
Granted
Sep 2, 2014
Kind
B2
Abstract

A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Claims (45)

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming an insulating layer over the substrate;

forming a recess in a first surface of the insulating layer;

forming a first interconnect structure in the recess and over the substrate;

disposing a first semiconductor die in the recess electrically connected to the first interconnect structure; and

disposing a second semiconductor die over the recess and first semiconductor die.

2. The method of claim 1 , further including providing a conductive pillar through the insulating layer.

3. The method of claim 1 , further including forming a conductive via through the substrate.

4. The method of claim 1 , further including forming the first interconnect structure to follow a contour of the recess.

5. The method of claim 1 , wherein the recess includes sloped or stepped sidewalls.

6. The method of claim 1 , further including forming a second interconnect structure over a second surface of the insulating layer opposite the first surface of the insulating layer.

7. A method of making a semiconductor device, comprising:

providing a substrate;

forming an insulating layer over the substrate;

forming a recess in a first surface of the insulating layer;

forming a first interconnect structure in the recess; and

disposing a first semiconductor die in the recess.

8. The method of claim 7 , further including disposing a second semiconductor die over the recess.

9. The method of claim 7 , further including providing a conductive pillar through the insulating layer.

10. The method of claim 7 , further including forming a conductive via through the substrate.

11. The method of claim 7 , further including forming the first interconnect structure to follow a contour of the recess.

12. The method of claim 7 , wherein the recess includes sloped or stepped sidewalls.

13. The method of claim 7 , further including forming a second interconnect structure over a second surface of the insulating layer opposite the first surface of the insulating layer.

14. A semiconductor device, comprising:

a substrate;

an insulating layer formed over the substrate with a recess in a first surface of the insulating layer;

a first interconnect structure formed in the recess;

a first semiconductor die disposed in the recess; and

a second semiconductor die disposed over the recess and first semiconductor die.

15. The semiconductor device of claim 14 , further including a conductive pillar through the insulating layer.

16. The semiconductor device of claim 14 , further including a conductive via formed through the substrate.

17. The semiconductor device of claim 14 , wherein the first semiconductor die is electrically coupled to the first interconnect structure.

18. The semiconductor device of claim 14 , wherein the recess includes sloped or stepped sidewalls.

19. The semiconductor device of claim 14 , further including a second interconnect structure formed over a second surface of the insulating layer opposite the first surface of the insulating layer.

20. A semiconductor device, comprising:

a substrate;

an insulating layer formed over the substrate with a recess in a first surface of the insulating layer;

a first interconnect structure formed in the recess; and

a first semiconductor die disposed in the recess.

21. The semiconductor device of claim 20 , further including a second semiconductor die disposed over the recess.

22. The semiconductor device of claim 20 , further including a conductive pillar through the insulating layer.

23. The semiconductor device of claim 20 , further including a conductive via formed through the substrate.

24. The semiconductor device of claim 20 , wherein the recess includes sloped or stepped sidewalls.

25. The semiconductor device of claim 20 , further including a second interconnect structure formed over a second surface of the insulating layer opposite the first surface of the insulating layer.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE ASSIGNEE'S NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064805/0735 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE. " TO STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0391. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064809/0877 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0391 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0161 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Continuity (2)
Continuation 12780268 · May 14, 2010
Related Publication 20130292850A1 · Nov 7, 2013