Patent Assignment
Reel/Frame 038378/0161
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 8
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(56)
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
App. No. 14/258,300
→
Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure
App. No. 14/021,056
→
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
App. No. 13/935,963
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE DISPOSED IN A CAVITY OF AN INTERCONNECT STRUCTURE AND GROUNDED THROUGH THE DIE TSV
App. No. 13/935,312
→
SEMICONDUCTOR DEVICE WITH BUMP FORMED ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
App. No. 13/906,844
→
Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
App. No. 13/896,635
→
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
App. No. 13/870,928
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
App. No. 13/846,742
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
App. No. 13/769,302
→
LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
App. No. 13/766,646
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
App. No. 13/766,493
→
Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
App. No. 13/732,150
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
App. No. 13/714,061
→
Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
App. No. 13/691,440
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIFFERENT HEIGHT CONDUCTIVE PILLARS TO ELECTRICALLY INTERCONNECT STACKED LATERALLY OFFSET SEMICONDUCTOR DIE
App. No. 13/684,055
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
App. No. 13/679,792
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
App. No. 13/606,451
→
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer
App. No. 13/555,531
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING BUMPS FORMED ON SEMICONDUCTOR DIE INTO PENETRABLE ADHESIVE LAYER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
App. No. 13/536,177
→
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
App. No. 13/446,664
→
Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress
App. No. 13/438,402
→
Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure
App. No. 13/438,463
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME LEAD ARRAY ROUTING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/427,598
→
Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration
App. No. 13/426,576
→
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING SEMICONDUCTOR WAFER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY THROUGH MOUNTING TAPE
App. No. 13/426,416
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING OPENINGS AND TRENCHES IN INSULATING LAYER BY FIRST LDA AND SECOND LDA FOR RDL FORMATION
App. No. 13/426,561
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE LAYER OVER METAL SUBSTRATE FOR ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE
App. No. 13/425,349
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND MOLDED CAVITIES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/422,649
→
Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure
App. No. 13/356,485
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE MOLD GATE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/325,395
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
App. No. 13/312,852
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 13/284,654
→
Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
App. No. 13/235,413
→
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
App. No. 13/231,789
→
LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS
App. No. 13/195,973
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING TSV SEMICONDUCTOR DIE WITHIN ENCAPSULANT WITH TMV FOR VERTICAL INTERCONNECT IN POP
App. No. 13/098,440
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/085,475
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP STRUCTURE WITH INSULATING BUFFER LAYER TO REDUCE STRESS ON SEMICONDUCTOR WAFER
App. No. 13/037,181
→
Semiconductor Device and Method of Forming High Routing Density Bol Bonl and Bonp interconnect sites on substrate
App. No. 12/961,027
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PAD LAYOUT FOR FLIPCHIP SEMICONDUCTOR DIE
App. No. 12/959,709
→
Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die
App. No. 12/949,396
→
SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
App. No. 12/941,683
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SHIELD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/890,371
→
SEMICONDUCTOR DEVICE AND METHOD OF LASER-MARKING LAMINATE LAYER FORMED OVER EWLB WITH TAPE APPLIED TO OPPOSITE SURFACE
App. No. 12/889,588
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLES AND METHOD OF MANUFACTURE THEREOF
App. No. 12/884,102
→
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV
App. No. 12/852,433
→
Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die
App. No. 12/612,938
→
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
App. No. 12/606,351
→
Semiconductor Device and Method of Forming Adhesive Material to Secure Semiconductor Die to Carrier in WLCSP
App. No. 12/567,033
→
Semiconductor Device and Method of Forming Cavity in PCB Containing Encapsulant or Dummy Die Having CTE Similar to CTE of Large Array WLCSP
App. No. 12/557,763
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING TOPSIDE AND BOTTOM-SIDE INTERCONNECT STRUCTURES AROUND CORE DIE WITH TSV
App. No. 12/332,835
→
INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING CAVITY
App. No. 12/197,209
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD GATE
App. No. 12/192,042
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADS HAVING MULTIPLE SIDES EXPOSED
App. No. 12/014,578
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING RESILIENT MEMBER MOLD SYSTEM TECHNOLOGY
App. No. 11/749,717
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WINDOW OPENING
App. No. 11/465,744
→