IP Library Granted Patent US 8,932,908
Granted Patent B2
US 8,932,908 · App. 13/896,635 · Granted Jan 13, 2015

Semiconductor device and method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die

Inventors: KyuWon Lee (Kyoungki-Do, KR); HyunSu Shin (Incheon, KR); Hun Jeong (Seoul, KR); JinGwan Kim (Seoul, KR); SunYoung Chun (Kyoungki-Do, KR)
Assignee: STATS ChipPAC, Ltd.
H01L21/52H01L21/563H01L24/16H01L24/17H01L24/81H01L24/94H01L25/105H01L25/50H01L23/48H01L24/10H01L23/3128H01L2224/13099H01L2224/16145H01L2224/16225H01L2224/1718H01L2224/73204H01L2224/83102H10L2224/92125H01L2224/94H01L2225/1023H01L2225/1058H01L2924/01013H01L2924/01029H01L2924/01047H01L2924/01049H01L2924/01073H01L2924/01079H01L2924/01082H01L2924/15311H01L2924/15331H01L2224/32225H01L2924/0105H01L2924/01074H01L2924/01322H01L2924/014H01L2924/13091H01L2224/48091H01L2224/73265
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Quick Facts
Patent No.
US 8,932,908
App. No.
13/896,635
Granted
Jan 13, 2015
Kind
B2
Abstract

A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.

Claims (65)

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer in a first surface of the substrate;

removing a portion of the first conductive layer to a level below the first surface of the substrate;

providing a semiconductor die including an interconnect structure formed over a surface of the semiconductor die; and

disposing the semiconductor die over the substrate with the interconnect structure contacting the first conductive layer and a sidewall of the substrate.

2. The method of claim 1 , wherein the interconnect structure includes a bump.

3. The method of claim 1 , wherein the first conductive layer is recessed 10-20 micrometers below the first surface of the substrate.

4. The method of claim 1 , further including forming an insulating layer over the first surface of the substrate.

5. The method of claim 1 , further including

depositing an underfill material between the semiconductor die and substrate.

6. The method of claim 1 , further including:

forming a conductive via through the substrate; and

forming a second conductive layer over a second surface of the substrate.

7. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer in a first surface of the substrate;

forming a recessed interconnect site by removing a portion of the first conductive layer to a level below the first surface of the substrate;

providing a semiconductor die including an interconnect structure formed over a surface of the semiconductor die; and

disposing the semiconductor die over the substrate with the interconnect structure contacting the recessed interconnect site.

8. The method of claim 7 , wherein the interconnect structure contacts a sidewall of the substrate above the recessed interconnect site.

9. The method of claim 7 , wherein the interconnect structure includes a bump.

10. The method of claim 7 , further including depositing an underfill material between the semiconductor die and substrate.

11. The method of claim 7 , wherein the first conductive layer is recessed 10-20 micrometers below the first surface of the substrate.

12. The method of claim 7 , further including:

forming a conductive via through the substrate; and

forming a second conductive layer over a second surface of the substrate.

13. The method of claim 12 , further including

stacking a plurality of semiconductor devices

and

electrically connecting the stacked semiconductor devices through the interconnect structure, first conductive layer, second conductive layer, and conductive via.

14. A semiconductor device, comprising:

a substrate; and

an interconnect site formed below a first surface of the substrate, the interconnect site including a first conductive layer etched below the first surface of the substrate to form a recess in the substrate with a sidewall of the recess extending from the etched first conductive layer to the first surface of the substrate.

15. The semiconductor device of claim 14 , further including a semiconductor die disposed over the substrate and electrically connected to the interconnect site.

16. The semiconductor device of claim 15 , further including a bump disposed between the semiconductor die and the interconnect site.

17. The semiconductor device of claim 15 , further including an underfill material deposited between the semiconductor die and substrate.

18. The semiconductor device of claim 14 , wherein the first conductive layer is recessed 10-20 micrometers below the first surface of the substrate.

19. The semiconductor device of claim 15 , further including:

a conductive via formed through the substrate; and

a second conductive layer formed over a second surface of the substrate.

20. The semiconductor device of claim 19 , further including:

a plurality of bumps disposed between the semiconductor die and substrate; and

a plurality of stacked semiconductor devices electrically connected through the bumps, first conductive layer, second conductive layer, and conductive via.

21. A semiconductor device, comprising:

a substrate;

an interconnect site formed below a surface of the substrate, the interconnect site including a first conductive layer etched below opposing sidewalls of a recess in the substrate;

a semiconductor die disposed over the substrate; and

an interconnect structure disposed between the semiconductor die and interconnect site.

22. The semiconductor device of claim 21 , wherein the interconnect structure contacts the opposing sidewalls of the recess in the substrate.

23. The semiconductor device of claim 21 , wherein the first conductive layer is recessed 10-20 micrometers below the surface of the substrate.

24. The semiconductor device of claim 21 , further including an insulating layer formed over the surface of the substrate.

25. The semiconductor device of claim 21 , further including an underfill material deposited between the semiconductor die and substrate.

26. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer in a first surface of the substrate; and

forming an interconnect site for the substrate recessed below the first surface of the substrate by removing a portion of the first conductive layer.

27. The method of claim 26 , further including:

providing a semiconductor die including an interconnect structure formed over a surface of the semiconductor die; and

disposing the semiconductor die over the substrate with the interconnect structure contacting the interconnect site.

28. The method of claim 26 , further including depositing an underfill material between the semiconductor die and substrate.

29. The method of claim 26 , wherein the interconnect structure includes a bump.

30. The method of claim 26 , further including:

forming a conductive via through the substrate; and

forming a second conductive layer over a second surface of the substrate.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE. " TO STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0391. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064809/0877 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE ASSIGNEE'S NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064805/0735 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052963/0546 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0360 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0161 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0391 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Continuity (3)
Continuation 13606631 · Sep 7, 2012
Division 12951399 · Nov 22, 2010
Related Publication 20130249090A1 · Sep 26, 2013