IP Library › Assignment 052844/0491
Patent Assignment
Reel/Frame 052844/0491

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-04 Received: 2020-06-04 Pages: 31
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (100)
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
App. No. 14/258,300
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP
App. No. 14/043,751
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MOLD UNDERFILL USING DISPENSING NEEDLE HAVING SAME WIDTH AS SEMICONDUCTOR DIE
App. No. 14/020,996
→
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
App. No. 13/935,963
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE DISPOSED IN A CAVITY OF AN INTERCONNECT STRUCTURE AND GROUNDED THROUGH THE DIE TSV
App. No. 13/935,312
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRENCHED LEADFRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 13/934,797
→
METHODS OF FORMING SOLDER BALLS IN SEMICONDUCTOR PACKAGES
App. No. 13/931,295
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LOW PROFILE 3D FAN-OUT PACKAGE
App. No. 13/931,397
→
SEMICONDUCTOR DEVICE WITH BUMP FORMED ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
App. No. 13/906,844
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFINING CONDUCTIVE BUMP MATERIAL DURING REFLOW WITH SOLDER MASK PATCH
App. No. 13/905,845
→
Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
App. No. 13/896,635
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/896,608
→
METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND
App. No. 13/893,616
→
Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate
App. No. 13/870,928
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION
App. No. 13/846,742
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF
App. No. 13/791,375
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING
App. No. 13/769,302
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
App. No. 13/768,862
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
App. No. 13/766,493
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
App. No. 13/760,187
→
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
App. No. 13/756,817
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/742,580
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/740,151
→
SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
App. No. 13/727,116
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
App. No. 13/714,061
→
Semiconductor Device and Method of Forming Conductive TSV With Insulating Annular Ring
App. No. 13/691,578
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 13/649,834
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
App. No. 13/606,451
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/597,086
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ARRAY CONTACTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/586,178
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE
App. No. 13/563,598
→
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer
App. No. 13/555,531
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MOLD FLASH PREVENTION TECHNOLOGY
App. No. 13/536,382
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER
App. No. 13/536,268
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/536,321
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/528,051
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING WARPAGE PREVENTION STRUCTURES
App. No. 13/526,877
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA AND METHOD OF MANUFACTURE THEREOF
App. No. 13/517,897
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/495,663
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMALLY CONDUCTIVE LAYER BETWEEN SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE
App. No. 13/492,687
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTING MECHANISM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/490,908
→
INTEGRATED CIRCUIT PACKAGE WITH MOLDED CAVITY
App. No. 13/463,148
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 13/446,741
→
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
App. No. 13/446,664
→
ELECTRONIC SYSTEM WITH EXPANSION FEATURE
App. No. 13/441,550
→
Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress
App. No. 13/438,402
→
SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS
App. No. 13/429,119
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME LEAD ARRAY ROUTING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/427,598
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ULTRA-THIN CHIP AND METHOD OF MANUFACTURE THEREOF
App. No. 13/426,529
→
Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration
App. No. 13/426,576
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO-VIAS PARTIALLY THROUGH INSULATING MATERIAL OVER BUMP INTERCONNECT CONDUCTIVE LAYER FOR STRESS RELIEF
App. No. 13/426,552
→
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING SEMICONDUCTOR WAFER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY THROUGH MOUNTING TAPE
App. No. 13/426,416
→
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
App. No. 13/423,262
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND MOLDED CAVITIES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/422,649
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
App. No. 13/405,094
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 13/367,214
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DIE
App. No. 13/366,560
→
Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure
App. No. 13/356,485
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 13/345,589
→
SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
App. No. 13/339,185
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PERIMETER ANTIWARPAGE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/327,651
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/327,529
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF
App. No. 13/325,359
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT CONDUCTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/325,530
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE MOLD GATE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/325,395
→
Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
App. No. 13/324,349
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers
App. No. 13/312,852
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
App. No. 13/306,768
→
SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS
App. No. 13/303,019
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER-LEVEL MULTI-ROW ETCHED LEADFRAME WITH BASE LEADS AND EMBEDDED SEMICONDUCTOR DIE
App. No. 13/284,811
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 13/284,654
→
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
App. No. 13/248,312
→
SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 13/245,099
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXTERNAL WIRE CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/244,262
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/243,886
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/244,273
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK DEVICE
App. No. 13/243,699
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/242,656
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/237,918
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STACKED SEMICONDUCTOR DIE AND CONDUCTIVE INTERCONNECT STRUCTURE THROUGH AN ENCAPSULANT
App. No. 13/234,902
→
Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level
App. No. 13/231,839
→
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
App. No. 13/218,653
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/197,070
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
App. No. 13/197,215
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LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS
App. No. 13/195,973
→
LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/195,465
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SEMICONDUCTOR PACKAGE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO OPPOSITE SIDES OF TSV SUBSTRATE
App. No. 13/191,386
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/188,456
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY
App. No. 13/187,252
→
Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof
App. No. 13/181,838
→
FLIP CHIP INTERCONNECTION STRUCTURE
App. No. 13/175,694
→
Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street
App. No. 13/171,341
→
WAFER LEVEL DIE INTEGRATION AND METHOD THEREFOR
App. No. 13/170,116
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Semiconductor Device and Method of Forming EWLB Package With Standoff Conductive Layer Over Encapsulant Bumps
App. No. 13/167,133
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/167,631
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEAD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/167,458
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/166,809
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/166,802
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/165,658
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/163,611
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