IP Library › Granted Patent US 8,896,133
Granted Patent Utility
US 8,896,133 · Confirmation No. 8728

Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate

Applicant: STATS CHIPPAC, LTD.
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2016-04-07 OATH Oath or Declaration filed 8 View
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2014-11-05 ISSUE.NTF Issue Notification 1 View
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2014-07-22 SRFW Search information including classification, databases and other search related notes 1 View
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2014-07-22 FWCLM Index of Claims 1 View
2014-06-26 RCEX Request for Continued Examination (RCE) 3 View
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2014-03-27 CTFR Final Rejection 9 View
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2014-03-27 892 List of references cited by examiner 1 View
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2014-03-27 SRFW Search information including classification, databases and other search related notes 1 View
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2014-02-09 DISQ Terminal Disclaimer review decision 1 View
2014-01-15 A... Amendment/Request for Reconsideration-After Non-Final Rejection 1 View
2014-01-15 SPEC Specification 1 View
2014-01-15 CLM Claims 6 View
2014-01-15 REM Applicant Arguments/Remarks Made in an Amendment 7 View
2014-01-15 DIST Terminal Disclaimer Filed 1 View
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2014-01-15 N417 Electronic Filing System Acknowledgment Receipt 2 View
2014-01-15 WFEE Fee Worksheet (SB06) 1 View
2013-10-16 CTNF Non-Final Rejection 9 View
2013-10-16 892 List of references cited by examiner 1 View
2013-10-16 SRFW Search information including classification, databases and other search related notes 1 View
2013-10-16 SRNT Examiner's search strategy and results 5 View
2013-10-16 1449 List of References cited by applicant and considered by examiner 12 View
2013-10-16 FWCLM Index of Claims 1 View
2013-09-12 NTC.PUB Notice of Publication 1 View
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2013-04-25 N417 Electronic Filing System Acknowledgment Receipt 2 View
2013-04-25 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
Patent No.
US 8,896,133
App. No.
13/870,928
Filed
2013-04-25
Granted
2014-11-25
Pub. No.
US20130234324A1
Examiner
HA, NATHAN W
Art Unit
2814
PTA
0 days