IP Library › Assignment 053511/0298

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Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die

App. No. 13/886,556

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Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP

App. No. 13/887,180

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Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

App. No. 13/874,150

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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL

App. No. 13/871,157

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Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate

App. No. 13/870,928

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS

App. No. 13/853,969

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION

App. No. 13/846,742

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE

App. No. 13/846,014

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Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure

App. No. 13/845,329

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP

App. No. 13/832,333

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF

App. No. 13/782,618

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Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration

App. No. 13/771,825

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOLDING

App. No. 13/769,302

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES

App. No. 13/768,862

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LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT

App. No. 13/766,646

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE

App. No. 13/766,493

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Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)

App. No. 13/765,478

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME

App. No. 13/765,594

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL

App. No. 13/760,187

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Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die

App. No. 13/732,150

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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS

App. No. 13/728,012

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SEMICONDUCTOR DEVICE HAVING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS

App. No. 13/727,116

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE

App. No. 13/726,467

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Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection

App. No. 13/720,516

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME

App. No. 13/683,946

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Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding

App. No. 13/682,510

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SEMICONDUCTOR PACKAGE AND METHOD OF FORMING Z-DIRECTION CONDUCTIVE POSTS EMBEDDED IN STRUCTURALLY PROTECTIVE ENCAPSULANT

App. No. 13/682,281

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FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE

App. No. 13/645,397

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING

App. No. 13/622,297

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Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die

App. No. 13/609,050

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Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

App. No. 13/609,003

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Semiconductor Device and Method of Forming a Conductive Via-in-Via Structure

App. No. 13/604,539

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Semicinductor Device with Cross-Talk Isolation Using M-CAP

App. No. 13/572,517

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Semiconductor Device and Method of Forming WLCSP Structure using Protruded MLP

App. No. 13/570,979

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Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield

App. No. 13/569,088

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Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit

App. No. 13/569,105

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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP

App. No. 13/566,287

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SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE THROUGH ORGANIC VIAS

App. No. 13/553,739

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Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die

App. No. 13/553,711

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL DIE INTEGRATION

App. No. 13/546,726

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Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus

App. No. 13/545,887

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Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Level Chip Scale Package

App. No. 13/543,088

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Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package

App. No. 13/543,637

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Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution

App. No. 13/536,120

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Solder Joint Flip Chip Interconnection Having Relief Structure

App. No. 13/529,794

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE

App. No. 13/478,008

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Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Semiconductor Die and Substrate

App. No. 13/476,410

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLAR HAVING AN EXPANDED BASE

App. No. 13/468,981

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Semiconductor Device Having a Vertical Interconnect Structure Using Stud Bumps

App. No. 13/446,863

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Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component

App. No. 13/438,696

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Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

App. No. 13/430,577

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Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars

App. No. 13/430,538

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Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration

App. No. 13/426,576

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Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces

App. No. 13/424,710

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Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound

App. No. 13/424,484

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE

App. No. 13/423,832

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPLIANT CONDUCTIVE INTERCONNECT STRUCTURE IN FLIPCHIP PACKAGE

App. No. 13/422,981

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY

App. No. 13/417,034

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Double-Sided Semiconductor Device and Method of Forming Top-Side and Bottom-Side Interconnect Structures

App. No. 13/408,715

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Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure

App. No. 13/366,008

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Semiconductor Device and Method of Forming Passive Devices

App. No. 13/365,097

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SEMICONDUCTOR DEVICE INCLUDING PRE-FABRICATED SHIELDING FRAME DISPOSED OVER SEMICONDUCTOR DIE

App. No. 13/350,692

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING EXTENDED SEMICONDUCTOR DEVICE WITH FAN-OUT INTERCONNECT STRUCTURE TO REDUCE COMPLEXITY OF SUBSTRATE

App. No. 13/336,860

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Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVs in Peripheral Region of the Die

App. No. 13/334,556

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Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief

App. No. 13/333,395

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP

App. No. 13/326,128

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER

App. No. 13/324,446

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Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate

App. No. 13/324,397

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Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate

App. No. 13/324,349

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SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE

App. No. 13/314,984

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP

App. No. 13/315,010

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING GUARD RING AROUND CONDUCTIVE TSV THROUGH SEMICONDUCTOR WAFER

App. No. 13/315,033

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Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

App. No. 13/312,730

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SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS

App. No. 13/303,019

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Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer

App. No. 13/289,811

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SEMICONDUCTOR DIE AND METHOD OF FORMING SLOPED SURFACE IN PHOTORESIST LAYER TO ENHANCE FLOW OF UNDERFILL MATERIAL BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE

App. No. 13/287,006

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMAL INTERFACE MATERIAL AND HEAT SPREADER OVER SEMICONDUCTOR DIE

App. No. 13/287,035

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Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers

App. No. 13/284,003

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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF

App. No. 13/242,656

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE

App. No. 13/239,080

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR PACKAGE USING PANEL FORM CARRIER

App. No. 13/236,952

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Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structure

App. No. 13/234,366

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Semiconductor Device and Method of Forming a Low Profile Dual-Purpose Shield and Heat-Dissipation Structure

App. No. 13/226,767

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Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheral region of semiconductor die

App. No. 13/225,683

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Semiconductor Device and Method of Forming TIM Within Recesses of MUF Material

App. No. 13/218,388

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Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures

App. No. 13/208,027

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Semiconductor Device and Method of Forming POP With Stacked Semiconductor Die and Bumps Formed Directly on the Lower Die

App. No. 13/195,636

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV INTERPOSER WITH SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE ON OPPOSING SURFACES OF THE INTERPOSER

App. No. 13/184,253

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE COATING OVER INTERCONNECT STRUCTURE TO INHIBIT SURFACE OXIDATION

App. No. 13/167,566

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Semiconductor Device and Method of Forming RF FEM and RF Transceiver in Semiconductor Package

App. No. 13/163,026

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Semiconductor Device and Method of Forming 3D Semiconductor Package with Semiconductor Die Stacked Over Semiconductor Wafer

App. No. 13/112,172

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Semiconductor Device and Method of Forming Dummy Pillars Between Semiconductor Die and Substrate for Maintaining Standoff Distance

App. No. 13/107,075

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SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME WITH CONDUCTIVE BODIES FOR VERTICAL ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE

App. No. 13/106,591

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Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

App. No. 13/098,438

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Semiconductor Device and Method of Forming an Interconnect Structure with Conductive Material Recessed Within Conductive Ring Over Surface of Conductive Pillar

App. No. 13/098,448

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Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer

App. No. 13/098,443

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Semiconductor Device and Method of Forming Leadframe With Notched Fingers for Stacking Semiconductor Die

App. No. 13/069,191

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Semiconductor Device and Method of Forming Openings Through Insulating Layer Over Encapsulant for Enhanced Adhesion of Interconnect Structure

App. No. 12/964,823

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METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE

App. No. 12/951,399

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Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die

App. No. 12/870,681

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