Semiconductor device and method of forming integrated passive device
View Patent ↗An IPD semiconductor device has a capacitor formed over and electrically connected to a semiconductor die. An encapsulant is deposited over the capacitor and around the semiconductor die. A first interconnect structure is formed over a first surface of the encapsulant by forming a first conductive layer, forming a first insulating layer over the first conductive layer, and forming a second conductive layer over the first insulating layer. The second conductive layer has a portion formed over the encapsulant at least 50 micrometer away from a footprint of the semiconductor die and wound to operate as an inductor. The portion of the second conductive layer is electrically connected to the capacitor by the first conductive layer. A second interconnect structure is formed over a second surface of the encapsulant. A conductive pillar is formed within the encapsulant between the first and second interconnect structures.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a first capacitor over a major surface of the semiconductor die as a plurality of conductive layers over opposing surfaces of an insulating layer;
depositing an encapsulant over the first capacitor and around the semiconductor die; and then
forming a first interconnect structure over the semiconductor die and a first surface of the encapsulant, the first interconnect structure including a first conductive layer wound to exhibit an inductive property and disposed a predetermined distance outside a vertical projection of a footprint of the semiconductor die.
2. The method of claim 1 , wherein the first conductive layer is disposed at least 50 micrometers away from the footprint of the semiconductor die.
3. The method of claim 1 , further including forming a second capacitor within the first interconnect structure.
4. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a capacitor over the semiconductor die;
depositing an encapsulant over the capacitor and around the semiconductor die;
forming a first interconnect structure over the semiconductor die and a first surface of the encapsulant, the first interconnect structure including a first inductor disposed a predetermined distance away from a vertical projection of a footprint of the semiconductor die; and
forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant.
5. The method of claim 4 , further including forming a second inductor within the second interconnect structure.
6. The method of claim 4 , further including forming a conductive pillar through the encapsulant between the first interconnect structure and second interconnect structure.
7. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a first capacitor over the semiconductor die;
depositing an encapsulant over the first capacitor and around the semiconductor die; and
forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure including a first conductive layer wound to exhibit an inductive property and disposed outside a footprint of the semiconductor die.
8. The method of claim 7 , wherein the first conductive layer is disposed at least 50 micrometers away from the footprint of the semiconductor die.
9. The method of claim 7 , further including forming a second capacitor within the first interconnect structure.
10. The method of claim 7 , further including forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant.
11. The method of claim 10 , further including forming a second inductor within the second interconnect structure.
12. The method of claim 10 , further including forming a conductive pillar through the encapsulant between the first interconnect structure and second interconnect structure.
13. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around the semiconductor die; and
forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure including an integrated passive device (IPD) disposed outside a footprint of the semiconductor die.
14. The method of claim 13 , wherein the IPD includes an inductor.
15. The method of claim 13 , wherein the IPD is disposed at least 50 micrometers away from the footprint of the semiconductor die.
16. The method of claim 13 , further including forming a capacitor over the semiconductor die.
17. The method of claim 13 , further including forming a capacitor within the first interconnect structure.
18. The method of claim 13 , further including:
forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant; and
forming a conductive pillar through the encapsulant between the first interconnect structure and second interconnect structure.
19. The method of claim 18 , further including forming a second inductor within the second interconnect structure.
20. A semiconductor device, comprising:
a semiconductor die;
a capacitor formed over the semiconductor die;
an encapsulant deposited over the capacitor and around the semiconductor die; and
a first interconnect structure formed over a first surface of the encapsulant, the first interconnect structure including an integrated passive device (IPD) disposed outside a footprint of the semiconductor die.
21. The semiconductor device of claim 20 , wherein the IPD includes an inductor.
22. The semiconductor device of claim 20 , wherein the IPD is disposed at least 50 micrometers away from the footprint of the semiconductor die.
23. The semiconductor device of claim 20 , further including:
a second interconnect structure formed over a second surface of the encapsulant opposite the first surface of the encapsulant; and
a conductive pillar formed through the encapsulant between the first interconnect structure and second interconnect structure.