Patent Assignment
Reel/Frame 038378/0427
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 8
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(79)
Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield
App. No. 13/569,088
→
Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit
App. No. 13/569,105
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
App. No. 13/566,287
→
SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE
App. No. 13/555,353
→
SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE THROUGH ORGANIC VIAS
App. No. 13/553,739
→
Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die
App. No. 13/553,711
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL DIE INTEGRATION
App. No. 13/546,726
→
Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer
App. No. 13/543,618
→
Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Level Chip Scale Package
App. No. 13/543,088
→
Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package
App. No. 13/543,637
→
Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution
App. No. 13/536,120
→
Solder Joint Flip Chip Interconnection Having Relief Structure
App. No. 13/529,794
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Semiconductor Die and Substrate
App. No. 13/476,410
→
SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING THIN SEMICONDUCTOR WAFER ON CARRIER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY
App. No. 13/469,754
→
Semiconductor Device Having a Vertical Interconnect Structure Using Stud Bumps
App. No. 13/446,863
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING B-STAGE CONDUCTIVE POLYMER OVER CONTACT PADS OF SEMICONDUCTOR DIE IN FO-WLCSP
App. No. 13/438,713
→
Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component
App. No. 13/438,696
→
Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices
App. No. 13/430,577
→
Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars
App. No. 13/430,538
→
Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound
App. No. 13/424,484
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NO-FLOW UNDERFILL MATERIAL AROUND VERTICAL INTERCONNECT STRUCTURE
App. No. 13/423,782
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
App. No. 13/423,832
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING IPD ON MOLDED SUBSTRATE
App. No. 13/423,265
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPEN CAVITY IN TSV INTERPOSER TO CONTAIN SEMICONDUCTOR DIE IN WLCSMP
App. No. 13/420,400
→
Double-Sided Semiconductor Device and Method of Forming Top-Side and Bottom-Side Interconnect Structures
App. No. 13/408,715
→
Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
App. No. 13/403,889
→
Semiconductor Device with Thin Profile WLCSP with Vertical Interconnect over Package Footprint
App. No. 13/403,859
→
Semiconductor Device and Method of Forming Passive Devices
App. No. 13/365,097
→
SEMICONDUCTOR DEVICE INCLUDING PRE-FABRICATED SHIELDING FRAME DISPOSED OVER SEMICONDUCTOR DIE
App. No. 13/350,692
→
Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring
App. No. 13/346,415
→
Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVs in Peripheral Region of the Die
App. No. 13/334,556
→
Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers
App. No. 13/284,003
→
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
App. No. 13/237,828
→
Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
App. No. 13/235,413
→
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
App. No. 13/231,789
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
App. No. 13/191,318
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE
App. No. 13/190,339
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV INTERPOSER WITH SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE ON OPPOSING SURFACES OF THE INTERPOSER
App. No. 13/184,253
→
Semiconductor Device and Method of Forming RDL over Contact Pad with High Alignment Tolerance or Reduced Interconnect Pitch
App. No. 13/181,412
→
Semiconductor Device and Method of Wafer Level Package Integration
App. No. 13/172,680
→
Semiconductor Device and Method of Forming 3D Semiconductor Package with Semiconductor Die Stacked Over Semiconductor Wafer
App. No. 13/112,172
→
Semiconductor Device and Method of Forming Dummy Pillars Between Semiconductor Die and Substrate for Maintaining Standoff Distance
App. No. 13/107,075
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME WITH CONDUCTIVE BODIES FOR VERTICAL ELECTRICAL INTERCONNECT OF SEMICONDUCTOR DIE
App. No. 13/106,591
→
Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP
App. No. 13/098,438
→
Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame
App. No. 13/098,419
→
Semiconductor Device and Method of Forming an Interconnect Structure with Conductive Material Recessed Within Conductive Ring Over Surface of Conductive Pillar
App. No. 13/098,448
→
Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
App. No. 13/098,443
→
Semiconductor Device and Method of Forming Leadframe With Notched Fingers for Stacking Semiconductor Die
App. No. 13/069,191
→
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
App. No. 13/038,843
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLCSP STRUCTURE USING PROTRUDED MLP
App. No. 13/032,536
→
Semiconductor Device with Bump Interconnection
App. No. 12/985,559
→
Semiconductor Device and Method of Forming Flipchip Interconnection Structure with Bump on Partial Pad
App. No. 12/969,451
→
Semiconductor Device and Method of Forming Openings Through Insulating Layer Over Encapsulant for Enhanced Adhesion of Interconnect Structure
App. No. 12/964,823
→
Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings
App. No. 12/961,107
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPENINGS THROUGH ENCAPSULANT TO REDUCE WARPAGE AND STRESS ON SEMICONDUCTOR PACKAGE
App. No. 12/961,260
→
METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE
App. No. 12/951,399
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FLIPCHIP INTERCONNECT STRUCTURE
App. No. 12/947,414
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERPOSER FOR STACKING AND ELECTRICALLY CONNECTING SEMICONDUCTOR DIE
App. No. 12/914,878
→
Stackable Package By Using Internal Stacking Modules
App. No. 12/882,748
→
Chip Scale Module Package in BGA Semiconductor Package
App. No. 12/882,728
→
Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
App. No. 12/870,681
→
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
App. No. 12/837,562
→
Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure
App. No. 12/822,458
→
Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die
App. No. 12/794,598
→
Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die
App. No. 12/792,031
→
Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP
App. No. 12/786,008
→
METHOD OF FORMING PERFORATED OPENING IN BOTTOM SUBSTRATE OF FLIPCHIP POP ASSEMBLY TO REDUCE BLEEDING OF UNDERFILL MATERIAL
App. No. 12/781,754
→
Semiconductor Device and Method of Forming Channels in Back Surface of FO-WLCSP for Heat Dissipation
App. No. 12/773,669
→
Semiconductor Device and Method of Forming Openings in Thermally-Conductive Frame of FO-WLCSP to Dissipate Heat and Reduce Package Height
App. No. 12/766,607
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PACKAGE-ON-PACKAGE STRUCTURE ELECTRICALLY INTERCONNECTED THROUGH TSV IN WLCSP
App. No. 12/717,335
→
Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
App. No. 12/714,190
→
Method of Forming Protective Material Between Semiconductor Die Stacked on Semiconductor Wafer to Reduce Defects During Singulation
App. No. 12/617,877
→
Semiconductor Device and Method of Forming Pre-Molded Semiconductor Die Having Bumps Embedded in Encapsulant
App. No. 12/551,270
→
Semiconductor Device and Method of Forming Dual-Active Sided Semiconductor Die in Fan-Out Wafer Level Chip Scale Package
App. No. 12/545,390
→
Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton
App. No. 12/505,273
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED DEVICE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,557
→
MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS
App. No. 12/055,665
→
FLIP CHIP INTERCONNECTION
App. No. 11/435,305
→
PHOTOCHROMIC POLYMERIZABLE COMPOSITIONS
App. No. 10/270,622
→