IP Library Granted Patent US 9,685,495
Granted Patent B2
US 9,685,495 · App. 13/423,265 · Granted Jun 20, 2017

Semiconductor device and method of forming IPD on molded substrate

Inventor: Yaojian Lin (Singapore, SG)
Assignee: STATS ChipPAC, Pte. Ltd.
H01L28/10H01L23/145H01L23/49822H01L23/642H01L23/645H01L27/016H01L28/24H01L28/60H01L23/5223H01L23/5227H01L24/48H01L2224/0401H01L2224/04042H01L2224/16H01L2224/48091H01L2224/48247H01L2224/48463H01L2224/73207H01L2924/00014H01L2924/01004H01L2924/01013H01L2924/01029H01L2924/01046H01L2924/01078H01L2924/01079H01L2924/01322H01L2924/04941H01L2924/09701H01L2924/12041H01L2924/13091H01L2924/14H01L2924/1433H01L2924/15311H01L2924/181H01L2924/19041
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Quick Facts
Patent No.
US 9,685,495
App. No.
13/423,265
Granted
Jun 20, 2017
Kind
B2
Abstract

A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.

Claims (57)

1. A method of making a semiconductor device, comprising:

disposing a first conductive layer in a mold;

forming a substrate by curing a molding compound in the mold over the first conductive layer;

forming a first insulating layer over the first conductive layer;

forming a second conductive layer over the first insulating layer to form a capacitor with the first conductive layer; and

forming an interconnect structure electrically connected to the second conductive layer.

2. The method of claim 1 , further including forming a resistive layer over the first conductive layer.

3. The method of claim 1 , wherein forming the interconnect structure includes forming a bump or bond wire electrically connected to the capacitor.

4. The method of claim 1 , further including depositing the molding compound between a first plate and second plate of the mold.

5. The method of claim 4 , further including:

applying a first releasable layer over the first plate; and

applying a second releasable layer over the second plate.

6. The method of claim 1 , further including forming a third conductive layer over the substrate and wound to exhibit inductive properties.

7. A method of making a semiconductor device, comprising:

disposing a second conductive layer in a mold;

forming a molded substrate by curing an encapsulant in the mold over the second conductive layer;

forming a first insulating layer over the molded substrate and second conductive layer;

forming a first conductive layer over the first insulating layer and wound to exhibit inductive properties; and

forming an interconnect structure over the first conductive layer opposite the molded substrate with the interconnect structure electrically connected to the first conductive layer.

8. The method of claim 7 , further including:

forming a second insulating layer over the second conductive layer; and

forming a third conductive layer over the second insulating layer and second conductive layer as a capacitor.

9. The method of claim 8 , further including forming a resistive layer over the second conductive layer.

10. The method of claim 8 , wherein a coefficient of thermal expansion of the molded substrate is similar to a coefficient of thermal expansion of the first conductive layer.

11. The method of claim 7 , wherein the interconnect structure includes a bump or bond wire.

12. The method of claim 7 , wherein forming the molded substrate includes:

providing the mold to include a first plate and a second plate;

forming a first releasable layer over the first plate;

forming a second releasable layer over the second plate;

forming the second conductive layer on the second releasable layer; and

depositing the encapsulant between the first plate and second plate of the mold.

13. A method of making a semiconductor device, comprising:

disposing a first conductive layer in a mold;

forming a substrate by curing a molding compound in the mold over the first conductive layer;

forming an integrated passive device (IPD) over the substrate after forming the substrate in the mold; and

forming an interconnect structure over the IPD.

14. The method of claim 13 , wherein forming the IPD includes forming a second conductive layer over the substrate and wound to exhibit inductive properties.

15. The method of claim 13 , wherein forming the IPD includes:

forming a first insulating layer over the first conductive layer; and

forming a second conductive layer over the first insulating layer and first conductive layer as a capacitor.

16. The method of claim 13 , further including forming a resistive layer over the first conductive layer.

17. The method of claim 13 , wherein a coefficient of thermal expansion of the substrate is similar to a coefficient of thermal expansion of the IPD.

18. The method of claim 13 , wherein the interconnect structure includes a bump or bond wire electrically connected to the IPD.

19. The method of claim 13 , wherein forming the substrate includes depositing an encapsulant between a first plate and second plate of the mold.

20. A semiconductor device, comprising:

a molded substrate;

a first conductive layer formed directly on the molded substrate and partially within a cavity of the molded substrate;

an integrated passive device (IPD) including the first conductive layer as a part of the IPD; and

an interconnect structure electrically connected to the IPD.

21. The semiconductor device of claim 20 , wherein the IPD further includes a second conductive layer formed over the molded substrate and wound to exhibit inductive properties.

22. The semiconductor device of claim 20 , wherein the IPD further includes:

a first insulating layer formed over the first conductive layer; and

a second conductive layer formed over the first insulating layer and first conductive layer as a capacitor.

23. The semiconductor device of claim 22 , further including a resistive layer formed over the first conductive layer.

24. The semiconductor device of claim 20 , further including:

a chase mold including a first plate and second plate; and

an encapsulant deposited between the first plate and second plate of the chase mold.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0427 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Continuity (2)
Continuation 12621738 · Nov 19, 2009
Related Publication 20120175735A1 · Jul 12, 2012