IP Library Patent Application 12505273
Patent Application
App. No. 12/505,273

Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton

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Quick Facts
Patent No.
US None
App. No.
12/505,273
Abstract

A semiconductor device is made by providing a semiconductor wafer having semiconductor die separated by a peripheral region. An opening is formed in the peripheral region having a depth less than a thickness of the wafer. A conductive material is deposited in the opening of the peripheral region of the wafer to form a conductive via extending partially through the wafer. The wafer is singulated through the conductive via in the peripheral region to provide a plurality of semiconductor die each having the conductive via. A semiconductor die is mounted on a sacrificial carrier. An encapsulant is deposited over the carrier around the semiconductor die. A portion of the encapsulant and semiconductor die is removed to expose the conductive via. A first and second interconnect structure are formed over the encapsulant and semiconductor die. The first and second interconnect structures are electrically connected to the conductive via.

Claims (66)

1 . A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die separated by a peripheral region;

forming an opening in the peripheral region having a depth less than a thickness of the semiconductor wafer;

depositing a conductive material in the opening of the peripheral region of the semiconductor wafer to form a conductive via extending partially through the semiconductor wafer;

singulating the semiconductor wafer through the conductive via in the peripheral region to provide a plurality of semiconductor die each having the conductive via;

leading with a first end of the conductive via, mounting a first semiconductor die on a sacrificial carrier;

depositing an encapsulant over the sacrificial carrier around the first semiconductor die;

removing a portion of the encapsulant and first semiconductor die to expose a second end of the conductive via;

forming a first interconnect structure over the encapsulant and a first surface of the first semiconductor die, the first interconnect structure being electrically connected to the second end of the conductive via;

removing the sacrificial carrier; and

forming a second interconnect structure over the encapsulant and a second surface of the first semiconductor die opposite the first surface of the first semiconductor die, the second interconnect structure being electrically connected to the first end of the conductive via.

2 . The method of claim 1 , further including mounting a second semiconductor die over the first interconnect structure.

3 . The method of claim 1 , further including:

forming a first redistribution layer between the conductive via and a contact pad of the first semiconductor die; and

forming a second redistribution layer over the first surface of the first semiconductor die, the second redistribution layer being electrically connected to the conductive via.

4 . The method of claim 1 , further including:

forming a first bump between the first end of the conductive via and second interconnect structure; and

forming a second bump between the second surface of the first semiconductor die and first interconnect structure.

5 . The method of claim 1 , further including forming the conductive via adjacent to a contact pad of the first semiconductor die.

6 . A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor components separated by a peripheral region;

forming an opening in the peripheral region having a depth less than a thickness of the semiconductor wafer;

depositing a conductive material in the opening of the peripheral region of the semiconductor wafer to form a conductive via;

singulating the semiconductor wafer through the conductive via in the peripheral region to provide a plurality of semiconductor components each having the conductive via;

mounting a first semiconductor component on a carrier;

depositing an encapsulant over the carrier around the first semiconductor component;

removing a portion of the encapsulant and first semiconductor component to expose the conductive via; and

forming a first interconnect structure over the encapsulant and first semiconductor component, the first interconnect structure being electrically connected to the conductive via.

7 . The method of claim 6 , further including:

removing the carrier; and

forming a second interconnect structure over the encapsulant and first semiconductor component opposite the first interconnect structure, the second interconnect structure being electrically connected to the conductive via.

8 . The method of claim 7 , further including forming a bump between the conductive via and second interconnect structure.

9 . The method of claim 7 , further including forming a bump between the first semiconductor die and first interconnect structure.

10 . The method of claim 6 , further including mounting a second semiconductor component over the first interconnect structure.

11 . The method of claim 6 , further including forming a redistribution layer between the conductive via and the first semiconductor component.

12 . The method of claim 6 , further including forming a redistribution layer between the first semiconductor component and first interconnect structure, the redistribution layer being electrically connected to the conductive via.

13 . The method of claim 6 , further including forming the conductive via adjacent to a contact pad of the first semiconductor component.

14 . A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor components separated by a peripheral region;

forming an opening in the peripheral region having a depth less than a thickness of the semiconductor wafer;

depositing a conductive material in the opening of the peripheral region of the semiconductor wafer to form a conductive via;

singulating the semiconductor wafer through the conductive via in the peripheral region to provide a plurality of semiconductor components each having the conductive via;

depositing an encapsulant around the first semiconductor component; and

forming a first interconnect structure over the encapsulant and first semiconductor component, the first interconnect structure being electrically connected to the conductive via.

15 . The method of claim 14 , further including forming a second interconnect structure over the encapsulant and first semiconductor component opposite the first interconnect structure, the second interconnect structure being electrically connected to the conductive via.

16 . The method of claim 15 , further including forming a bump between the conductive via and second interconnect structure.

17 . The method of claim 14 , further including mounting a second semiconductor component over the first interconnect structure.

18 . The method of claim 14 , further including forming a redistribution layer between the conductive via and first semiconductor component.

19 . The method of claim 14 , further including:

mounting the first semiconductor component on a carrier prior to depositing the encapsulant;

removing a portion of the encapsulant and first semiconductor component to expose the conductive via; and

removing the carrier after forming the first interconnect structure.

20 . A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor components separated by a peripheral region;

forming an opening in the peripheral region having a depth less than a thickness of the semiconductor wafer;

depositing a conductive material in the opening of the peripheral region of the semiconductor wafer to form a conductive via; and

singulating the semiconductor wafer through the conductive via in the peripheral region to provide a plurality of semiconductor components each having the conductive via.

21 . The method of claim 20 , further including:

mounting a first semiconductor component on a carrier;

depositing an encapsulant over the carrier around the first semiconductor component;

removing a portion of the encapsulant and first semiconductor component to expose the conductive via; and

forming a first interconnect structure over the encapsulant and first semiconductor component, the first interconnect structure being electrically connected to the conductive via.

22 . The method of claim 21 , further including mounting a second semiconductor component over the first interconnect structure.

23 . The method of claim 21 , further including forming a second interconnect structure over the encapsulant and first semiconductor component opposite the first interconnect structure, the second interconnect structure being electrically connected to the conductive via.

24 . The method of claim 23 , further including forming a bump between the conductive via and second interconnect structure.

25 . The method of claim 20 , further including forming a redistribution layer between the conductive via and first semiconductor component.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0427 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2009
From: DO, BYUNG TAI; PAGAILA, REZA A.
To: STATS CHIPPAC, LTD.
Reel/Frame 022972/0719 →