IP Library › Assignment 053476/0094
Patent Assignment
Reel/Frame 053476/0094

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-17 Received: 2020-06-17 Pages: 27
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (100)
FRAGRANCE EMANATION DEVICE WITH CAR VENT CLIP AND VISOR CLIP
App. No. 29/734,402
→
Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
App. No. 14/682,914
→
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
App. No. 14/637,054
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV
App. No. 14/600,825
→
Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die
App. No. 14/565,731
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
App. No. 14/341,578
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 13/243,474
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/242,306
→
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
App. No. 13/237,828
→
Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
App. No. 13/235,413
→
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
App. No. 13/231,789
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/211,303
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
App. No. 13/209,837
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP
App. No. 13/191,318
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE
App. No. 13/190,339
→
Semiconductor Device and Method of Wafer Level Package Integration
App. No. 13/172,680
→
Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame
App. No. 13/098,419
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEVELING STANDOFF AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,362
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INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/042,457
→
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
App. No. 13/038,843
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/039,309
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/038,384
→
Semiconductor Device with Bump Interconnection
App. No. 12/985,559
→
Semiconductor Device and Method of Forming Flipchip Interconnection Structure with Bump on Partial Pad
App. No. 12/969,451
→
Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings
App. No. 12/961,107
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FLIPCHIP INTERCONNECT STRUCTURE
App. No. 12/947,414
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/946,841
→
Stackable Package By Using Internal Stacking Modules
App. No. 12/882,748
→
Chip Scale Module Package in BGA Semiconductor Package
App. No. 12/882,728
→
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
App. No. 12/837,562
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/819,162
→
Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof
App. No. 12/813,335
→
Semiconductor Device and Method of Forming Ultra Thin Multi-Die Face-to-Face WLCSP
App. No. 12/786,008
→
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOF
App. No. 12/782,164
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METHOD OF FORMING PERFORATED OPENING IN BOTTOM SUBSTRATE OF FLIPCHIP POP ASSEMBLY TO REDUCE BLEEDING OF UNDERFILL MATERIAL
App. No. 12/781,754
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/777,615
→
Semiconductor Device and Method of Forming Channels in Back Surface of FO-WLCSP for Heat Dissipation
App. No. 12/773,669
→
Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
App. No. 12/763,378
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CARRIER SYSTEM WITH MULTI-TIER CONDUCTIVE POSTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/722,852
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/718,939
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INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH SHIELDING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/716,269
→
Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die
App. No. 12/714,190
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/714,291
→
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
App. No. 12/688,124
→
Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets
App. No. 12/683,008
→
Method of Forming Protective Material Between Semiconductor Die Stacked on Semiconductor Wafer to Reduce Defects During Singulation
App. No. 12/617,877
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/563,368
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/542,097
→
Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton
App. No. 12/505,273
→
Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate
App. No. 12/493,049
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INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/483,548
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,886
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/408,641
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Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
App. No. 12/407,949
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD BENEATH A SEMICONDUCTOR DIE WITH DIRECT CONNECTION TO EXTERNAL DEVICES
App. No. 12/332,253
→
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
App. No. 12/260,089
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-IN PACKAGE-ON-PACKAGE STRUCTURE USING THROUGH-SILICON VIAS
App. No. 12/209,838
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD OVER A HIGH-RESISTIVITY ENCAPSULANT SEPARATED FROM OTHER IPDS AND BASEBAND CIRCUIT
App. No. 12/205,755
→
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
App. No. 12/191,542
→
RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM
App. No. 12/182,132
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER GROUNDED THROUGH METAL PILLARS FORMED IN PERIPHERAL REGION OF THE SEMICONDUCTOR
App. No. 12/136,682
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INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/122,639
→
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
App. No. 12/062,403
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STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/056,402
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION
App. No. 12/055,612
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Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
App. No. 12/046,761
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System and Method for Proactively Establishing a Third-Party Payment Account for Services Rendered to a Resident of a Controlled-Environment Facility
App. No. 12/042,861
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Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
App. No. 11/964,397
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Wafer Level Package Integration and Method
App. No. 11/949,282
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE
App. No. 11/857,188
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SYSTEMS AND METHODS FOR REDUCING RECIDIVISM AMONG FORMER INMATES
App. No. 11/842,844
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INMATE MANAGEMENT AND CALL PROCESSING SYSTEMS AND METHODS
App. No. 11/777,168
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SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/772,776
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE
App. No. 11/767,820
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SYSTEMS AND METHODS FOR MANAGEMENT AND DISSEMINATION OF INFORMATION FROM A CONTROLLED ENVIRONMENT FACILITY
App. No. 11/810,691
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SELECTION OF A PARTICULAR COMMUNICATION CARRIER FROM A PLURALITY OF COMMUNICATION CARRIERS IN A SECURE ENVIRONMENT
App. No. 11/753,421
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE
App. No. 11/749,712
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SEMICONDUCTOR PACKAGE WIRE BONDING
App. No. 11/672,910
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WIRELESS COMMUNICATIONS CONTROL IN A CONTROLLED ENVIRONMENT FACILITY
App. No. 11/612,198
→
Solder joint flip chip interconnection
App. No. 11/640,468
→
SYSTEMS AND METHODS FOR GRAPHICALLY DISPLAYING AND ANALYZING CALL TREATMENT OPERATIONS
App. No. 11/562,842
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SYSTEM AND METHOD FOR REMOTE CALL FORWARD DETECTION USING SIGNALING
App. No. 11/562,887
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SCORE-DRIVEN MANAGEMENT OF RECORDINGS
App. No. 11/603,922
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SYSTEMS AND METHODS FOR VISITATION TERMINAL USER IDENTIFICATION
App. No. 11/562,784
→
SYSTEMS AND METHODS FOR CALL TREATMENT USING A THIRD PARTY DATABASE
App. No. 11/562,800
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SYSTEMS AND METHODS FOR RADIO FREQUENCY IDENTIFICATION
App. No. 11/562,855
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OPTIMIZING PROFITABILITY IN BUSINESS TRANSACTIONS
App. No. 11/562,829
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PROTECTED DATA CONTAINER FOR STORING DATA RELATING TO RECORDED CALLS IN A MANNER THAT ENABLES THE DATA TO BE AUTHENTICATED
App. No. 11/603,923
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SYSTEMS AND METHODS FOR REMOTE CALL REDIRECTION DETECTION AND TREATMENT
App. No. 11/562,763
→
SYSTEMS AND METHODS FOR DETECTING A CALL ANOMALY USING BIOMETRIC IDENTIFICATION
App. No. 11/603,960
→
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
App. No. 11/536,544
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/532,508
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BUMP FOR OVERHANG DEVICE
App. No. 11/469,307
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INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/458,065
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SYSTEMS AND METHODS FOR IDENTITY VERIFICATION USING CONTINUOUS BIOMETRIC MONITORING
App. No. 11/480,258
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SYSTEMS AND METHODS FOR MESSAGE DELIVERY IN A CONTROLLED ENVIRONMENT FACILITY
App. No. 11/480,289
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SYSTEMS AND METHODS FOR ACCOUNT ESTABLISHMENT AND TRANSACTION MANAGEMENT
App. No. 11/480,264
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INFORMATION DISSEMINATION SYSTEMS AND METHODS FOR USE IN A CONTROLLED ENVIRONMENT FACILITY
App. No. 11/479,950
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SYSTEMS AND METHODS FOR ACQUIRING, ACCESSING, AND ANALYZING INVESTIGATIVE INFORMATION
App. No. 11/479,990
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Epoxy Bump for Overhang Die
App. No. 11/420,853
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