Semiconductor device and method of forming stress relief layer between die and interconnect structure
A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.
1. A method of making a semiconductor device, comprising:
providing a plurality of conductive pillars;
disposing a semiconductor die between the conductive pillars;
depositing an encapsulant over the semiconductor die and around the conductive pillars;
forming a stress relief insulating layer over the semiconductor die and encapsulant;
forming a first interconnect structure over the stress relief insulating layer; and
forming a second interconnect structure over the encapsulant opposite the stress relief insulating layer, wherein the second interconnect structure includes an integrated passive device.
2. The method of claim 1 , wherein the first interconnect structure is electrically connected to the second interconnect structure through the conductive pillars.
3. The method of claim 1 , further including planarizing a back surface of the semiconductor die opposite an active surface of the semiconductor die with a surface of the encapsulant.
4. The method of claim 1 , wherein the stress relief insulating layer includes a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant.
5. A method of making a semiconductor device, comprising:
providing a conductive pillar;
disposing an adhesive layer over a semiconductor die;
disposing the semiconductor die including the adhesive layer adjacent to the conductive pillar;
removing the adhesive layer from the semiconductor die;
forming a stress relief insulating layer over the semiconductor die and conductive pillar;
forming a first interconnect structure over the stress relief insulating layer; and
forming a second interconnect structure over the semiconductor die opposite the stress relief insulating layer, wherein the second interconnect structure includes an integrated passive device.
6. The method of claim 5 , further including depositing an encapsulant over the semiconductor die and around the conductive pillar.
7. The method of claim 5 , wherein the first interconnect structure is electrically connected to the second interconnect structure through the conductive pillar.
8. The method of claim 5 , further including planarizing a back surface of the semiconductor die opposite an active surface of the semiconductor die with a surface of the conductive pillar.
9. The method of claim 5 , wherein the stress relief insulating layer includes a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive pillar.
10. The method of claim 9 , wherein:
the first thickness of the stress relief insulating layer includes a range of 5-100 μm; and
the second thickness of the stress relief insulating layer includes a range of 2-50 μm.
11. A method of making a semiconductor device, comprising:
providing a conductive pillar;
disposing a semiconductor die adjacent to the conductive pillar;
forming a stress relief insulating layer over the conductive pillar and contacting the semiconductor die; and
forming a first interconnect structure over the semiconductor die opposite the stress relief insulating layer, wherein the first interconnect structure includes an integrated passive device.
12. The method of claim 11 , further including forming a second interconnect structure over the stress relief insulating layer and electrically connected to the first interconnect structure through the conductive pillar.
13. The method of claim 11 , further including planarizing a back surface of the semiconductor die opposite an active surface of the semiconductor die with a surface of the conductive pillar opposite the stress relief insulating layer.
14. The method of claim 11 , wherein the stress relief insulating layer includes a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive pillar.
15. The method of claim 14 , wherein:
the first thickness of the stress relief insulating layer includes a range of 5-100 μm; and
the second thickness of the stress relief insulating layer includes a range of 2-50 μm.
16. A semiconductor device, comprising:
a semiconductor die;
a conductive pillar formed around the semiconductor die; and
a stress relief insulating layer formed over the semiconductor die and the conductive pillar including a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive pillar; and
a first interconnect structure formed over the semiconductor die opposite the stress relief insulating layer, wherein the first interconnect structure includes an integrated passive device.
17. The semiconductor device of claim 16 , wherein a back surface of the semiconductor die opposite an active surface of the semiconductor die is coplanar with a surface of the conductive pillar opposite the stress relief insulating layer.
18. The semiconductor device of claim 16 , wherein:
the first thickness of the stress relief insulating layer includes a range of 5-100 μm; and
the second thickness of the stress relief insulating layer includes a range of 2-50 μm.