Patent Assignment
Reel/Frame 038378/0442
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 8
Assignor
STATS CHIPPAC LD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(76)
Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
App. No. 14/682,914
→
Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
App. No. 14/637,054
→
Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die
App. No. 14/612,075
→
Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV
App. No. 14/600,825
→
Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die
App. No. 14/565,731
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
App. No. 14/341,578
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/211,303
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
App. No. 13/209,837
→
Semiconductor Device Having Embedded Integrated Passive Devices Electrically Interconnected Using Conductive Pillars
App. No. 13/048,771
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP BONDED DIES AND METHOD OF MANUFACTURE THEREOF
App. No. 13/039,309
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/038,384
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/819,162
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Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof
App. No. 12/813,335
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/777,615
→
Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process
App. No. 12/763,378
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PACKAGE-ON-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
App. No. 12/757,750
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PATTERNED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/714,291
→
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
App. No. 12/688,124
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Semiconductor Device and Method of Forming Double-Sided Through Vias in Saw Streets
App. No. 12/683,008
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/563,368
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/542,097
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Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate
App. No. 12/493,049
→
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH REDISTRIBUTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/483,548
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF
App. No. 12/412,886
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/408,641
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Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
App. No. 12/407,949
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD BENEATH A SEMICONDUCTOR DIE WITH DIRECT CONNECTION TO EXTERNAL DEVICES
App. No. 12/332,253
→
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
App. No. 12/260,089
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-IN PACKAGE-ON-PACKAGE STRUCTURE USING THROUGH-SILICON VIAS
App. No. 12/209,838
→
Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive Channels
App. No. 12/205,727
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN IPD OVER A HIGH-RESISTIVITY ENCAPSULANT SEPARATED FROM OTHER IPDS AND BASEBAND CIRCUIT
App. No. 12/205,755
→
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
App. No. 12/191,542
→
RDL PATTERNING WITH PACKAGE ON PACKAGE SYSTEM
App. No. 12/182,132
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER GROUNDED THROUGH METAL PILLARS FORMED IN PERIPHERAL REGION OF THE SEMICONDUCTOR
App. No. 12/136,682
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/122,639
→
Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
App. No. 12/062,403
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/056,402
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION
App. No. 12/055,612
→
Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
App. No. 12/046,761
→
Semiconductor Interconnect Structure with Stacked Vias Separated by Signal Line and Method Therefor
App. No. 12/035,843
→
Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
App. No. 11/964,397
→
Wafer Level Package Integration and Method
App. No. 11/949,282
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTI-CHIP MODULE
App. No. 11/857,188
→
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/772,776
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE
App. No. 11/767,820
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PERIMETER PADDLE
App. No. 11/749,712
→
SEMICONDUCTOR PACKAGE WIRE BONDING
App. No. 11/672,910
→
Solder joint flip chip interconnection
App. No. 11/640,468
→
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
App. No. 11/536,544
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/532,508
→
BUMP FOR OVERHANG DEVICE
App. No. 11/469,307
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/458,065
→
Epoxy Bump for Overhang Die
App. No. 11/420,853
→
SPACERLESS SEMICONDUCTOR PACKAGE CHIP STACKING SYSTEM
App. No. 11/383,802
→
Flip chip interconnect solder mask
App. No. 11/435,555
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/380,587
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DUAL ROW LEADFRAME AND FABRICATION METHOD
App. No. 11/379,740
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/379,097
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/279,741
→
Plasma display panel device with fluorescent layer protector
App. No. 11/397,018
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
App. No. 11/278,002
→
Flip chip interconnection having narrow interconnection sites on the substrate
App. No. 11/388,755
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/276,947
→
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM
App. No. 11/307,498
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INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING DIE-ATTACH PAD WITH ELEVATED BONDLINE THICKNESS
App. No. 11/307,349
→
INTEGRATED CIRCUIT SYSTEM WITH WAFERSCALE SPACER SYSTEM
App. No. 11/307,317
→
MICRO CHIP-SCALE-PACKAGE SYSTEM
App. No. 11/307,314
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INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE
App. No. 11/164,329
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED INTERLOCKING LEADFRAME
App. No. 11/163,556
→
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
App. No. 11/163,547
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STACKED DIE PACKAGING SYSTEM
App. No. 11/163,313
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SUBSTRATE INDEXING SYSTEM
App. No. 11/162,971
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HYPER THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/162,828
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INTEGRATED CIRCUIT PACKAGE WITH DIFFERENT HARDNESS BUMP PAD AND BUMP AND MANUFACTURING METHOD THEREFOR
App. No. 10/908,254
→
Under bump metallurgy in integrated circuits
App. No. 11/035,637
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Wire sweep resistant semiconductor package and manufacturing method thereof
App. No. 10/934,835
→