IP Library Granted Patent US 7,420,269
Granted Patent B2
US 7,420,269 · App. 11/379,097 · Granted Sep 2, 2008

Stacked integrated circuit package-in-package system

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Quick Facts
Patent No.
US 7,420,269
App. No.
11/379,097
Granted
Sep 2, 2008
Kind
B2
Abstract

A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first peripheral contact, forming a second integrated circuit package having a second peripheral contact, stacking the second integrated circuit package on the first integrated circuit package in an offset configuration with the first peripheral contact exposed, the offset configuration provides a second package overhang with the second integrated circuit package above the first integrated circuit package, electrically connecting the first peripheral contact and a package substrate top contact, and electrically connecting the second peripheral contact and the package substrate top contact.

Claims (65)

1. A stacked integrated circuit package-in-package system comprising:

forming a first integrated circuit package having a first peripheral contact;

forming a second integrated circuit package having a second peripheral contact;

stacking the second integrated circuit package on the first integrated circuit package in an offset configuration with the first peripheral contact exposed, the offset configuration provides a second package overhang with the second integrated circuit package above the first integrated circuit package;

electrically connecting the first peripheral contact and a package substrate top contact;

forming an integrated circuit die having a peripheral bond pad;

stacking the first integrated circuit package on an active side of the integrated circuit die in the offset configuration with the peripheral bond pad exposed and a first package overhang above the integrated circuit die; and

electrically connecting the peripheral bond pad and the package substrate top contact; and

electrically connecting the second peripheral contact and the package substrate top contact.

2. The system as claimed in claim 1 further comprising:

forming an integrated circuit die having a non-active side and an active side;

stacking the first integrated circuit package on the non-active side of the integrated circuit die; and

electrically connecting the active side and the package substrate top contact.

3. The system as claimed in claim 1 further comprising:

forming a package substrate having the package substrate top contact; and

connecting a component on the package substrate under the second package overhang.

4. The system as claimed in claim 1 further comprising:

forming the second integrated circuit package having a second package substrate, the second package substrate has an inner contact and the second peripheral contact;

forming an encapsulation having a recess to cover a portion of the second integrated circuit package, the recess exposes the inner contact; and

connecting a device on the inner contact in the recess.

5. A stacked integrated circuit package-in-package system comprising:

forming a first integrated circuit package having a first peripheral contact and a first encapsulation;

forming a second integrated circuit package having a second peripheral contact, an inner contact, and a second encapsulation;

stacking the second integrated circuit package on the first integrated circuit package in an offset configuration with the first peripheral contact and the second peripheral contact exposed, the offset configuration provides a second package overhang with the second integrated circuit package above the first integrated circuit package;

electrically connecting the first peripheral contact and a package substrate top contact; and

electrically connecting the second peripheral contact and the package substrate top contact.

6. The system as claimed in claim 5 further comprising electrically connecting the first peripheral contact and an inner row of package substrate top contacts.

7. The system as claimed in claim 5 further comprising electrically connecting the second peripheral contact and an outer row of package substrate top contacts.

8. The system as claimed in claim 5 further comprising:

forming first peripheral contacts on adjacent sides of the first integrated circuit package;

forming second peripheral contacts on adjacent sides of the second integrated circuit package; and

stacking the second integrated circuit package on the first integrated circuit package in an offset configuration with the first peripheral contacts and the second peripheral contacts exposed.

9. The system as claimed in claim 5 further comprising forming the first integrated circuit package system having a first inner contact and a first peripheral contact.

10. A stacked integrated circuit package-in-package system comprising:

an integrated circuit die having a peripheral bond pad;

a first integrated circuit package having a first peripheral contact, the first integrated circuit package on an active side of the integrated circuit die in the offset configuration with the peripheral bond pad exposed and a first package overhang above the integrated circuit die;

a second integrated circuit package having a second peripheral contact, the second integrated circuit package on the first integrated circuit package in an offset configuration with the first peripheral contact exposed, the offset configuration provides a second package overhang with the second integrated circuit package above the first integrated circuit package;

a first interconnect between the first peripheral contact and a package substrate top contact;

a second interconnect between the second peripheral contact and the package substrate top contact; and

a third interconnect between the peripheral bond pad and the package substrate top contact.

11. The system as claimed in claim 10 further comprising:

an integrated circuit die having a non-active side and an active side;

the first integrated circuit package on the non-active side the integrated circuit die; and

a third interconnect between the active side and the package substrate top contact.

12. The system as claimed in claim 10 further comprising:

a package substrate having the package substrate top contact; and

a component on the package substrate under the second package overhang.

13. The system as claimed in claim 10 further comprising:

the second integrated circuit package having a second package substrate, the second package substrate has an inner contact and the second peripheral contact;

an encapsulation having a recess to cover a portion of the second integrated circuit package, the recess exposes the inner contact; and

a device on the inner contact in the recess.

14. The system as claimed in claim 10 wherein:

the first integrated circuit package has the first peripheral contact and a first encapsulation;

the second integrated circuit package having the second peripheral contact;

the second integrated circuit package is on the first integrated circuit package in an offset configuration with the first peripheral contact and the second peripheral contact exposed, the offset configuration provides the second package overhang with the second integrated circuit package above the first integrated circuit package;

the first interconnect between the first peripheral contact and the package substrate top contact is a first bond wire;

the second interconnect between the second peripheral contact and the package substrate top contact is a second bond wire; and further comprising:

the second integrated circuit package having an inner contact and a second encapsulation.

15. The system as claimed in claim 14 further comprising the first interconnect between the first peripheral contact and an inner row of package substrate top contacts.

16. The system as claimed in claim 14 further comprising the second interconnect between the second peripheral contact and an outer row of package substrate top contacts.

17. The system as claimed in claim 14 further comprising:

first peripheral contacts on adjacent sides of the first integrated circuit package;

second peripheral contacts on adjacent sides of the second integrated circuit package; and

the second integrated circuit package on the first integrated circuit package in an offset configuration with the first peripheral contacts and the second peripheral contacts exposed.

18. The system as claimed in claim 14 further comprising the first integrated circuit package system having a first inner contact and a first peripheral contact.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052938/0305 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039980/0838 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0442 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2008
From: HA, JONG-WOO; KIM, GWANG; PARK, JUHYUN
To: STATS CHIPPAC LTD.
Reel/Frame 021570/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2006
From: HA, JONG-WOO; KIM, GWANG; PARK, JUHYUN
To: STATS CHIPPAC LTD.
Reel/Frame 017486/0717 →