Patent Assignment
Reel/Frame 064760/0986
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319)
Recorded: 2023-08-30
Received: 2023-08-30
Pages: 13
Assignor
STATS CHIPPAC PTE. LTE.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications
(91)
Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
App. No. 15/615,693
→
WETTING ENHANCEMENT COATING ON INTERMEDIATE TRANSFER MEMBER (ITM) FOR AQUEOUS INKJET INTERMEDIATE TRANSFER ARCHITECTURE
App. No. 14/219,125
→
THIN-FILM SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 13/940,643
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
App. No. 12/140,092
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 12/005,499
→
ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE
App. No. 11/934,654
→
CHIP CARRIER AND FABRICATION METHOD
App. No. 11/877,613
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING
App. No. 11/869,738
→
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIA ON SAW STREETS FORMED WITH PARTIAL SAW
App. No. 11/861,233
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH ANTI-MOLD FLASH FEATURE
App. No. 11/850,197
→
ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
App. No. 11/766,095
→
METHOD OF MAKING A WAFER LEVEL INTEGRATION PACKAGE
App. No. 11/765,930
→
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
App. No. 11/751,440
→
THROUGH-HOLE VIA ON SAW STREETS
App. No. 11/744,657
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/690,703
→
LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
App. No. 11/689,645
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
App. No. 11/671,684
→
METHOD OF FABRICATING A SHIELDED STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/615,922
→
INTEGRATED CIRCUIT PACKAGE WITH ELEVATED EDGE LEADFRAME
App. No. 11/610,304
→
SEMICONDUCTOR PACKAGE WITH CONTROLLED SOLDER BUMP WETTING
App. No. 11/562,957
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/558,404
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
App. No. 11/558,413
→
WIRE SWEEP RESISTANT SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
App. No. 11/530,802
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE
App. No. 11/463,505
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/462,537
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/462,320
→
LEADED STACKED PACKAGES HAVING ELEVATED DIE PADDLE
App. No. 11/459,557
→
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
App. No. 11/459,317
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STIFFENER
App. No. 11/456,544
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT SUPPORT
App. No. 11/456,532
→
METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH ETCHED RING AND DIE PADDLE
App. No. 11/428,272
→
MODULE HAVING STACKED CHIP SCALE SEMICONDUCTOR PACKAGES
App. No. 11/424,480
→
PACKAGE-ON-PACKAGE SYSTEM
App. No. 11/424,202
→
STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE
App. No. 11/420,873
→
OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/383,403
→
INTEGRATED CIRCUIT ENCAPSULATION SYSTEM WITH VENT
App. No. 11/383,038
→
MULTIPLE CHIP PACKAGE MODULE INCLUDING DIE STACKED OVER ENCAPSULATED PACKAGE
App. No. 11/381,901
→
OPTICAL DIE-DOWN QUAD FLAT NON-LEADED PACKAGE
App. No. 11/381,827
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWNSET LEAD
App. No. 11/381,734
→
INTEGRATED CIRCUIT LEADLESS PACKAGE SYSTEM
App. No. 11/381,726
→
METHOD OF FABRICATING A STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/380,596
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/379,097
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/379,106
→
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/396,954
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONNECTION PROTECTION
App. No. 11/278,421
→
SEMICONDUCTOR STACKED PACKAGE ASSEMBLY HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
App. No. 11/395,529
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD CLAMP LINE CRITICAL AREA HAVING WIDENED CONDUCTIVE TRACES
App. No. 11/278,343
→
SEMICONDUCTOR PACKAGE INCLUDING SECOND SUBSTRATE AND HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
App. No. 11/394,635
→
SEMICONDUCTOR ASSEMBLY INCLUDING CHIP SCALE PACKAGE AND SECOND SUBSTRATE WITH EXPOSED SURFACES ON UPPER AND LOWER SIDES
App. No. 11/397,027
→
MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
App. No. 11/394,363
→
CHIP CARRIER AND FABRICATION METHOD
App. No. 11/277,973
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/276,940
→
MULTICHIP PACKAGE SYSTEM
App. No. 11/276,948
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/276,946
→
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS
App. No. 11/276,681
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING
App. No. 11/307,861
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE INTERCONNECT INTERFACE
App. No. 11/307,862
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH RECESSED SPACER
App. No. 11/307,722
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
App. No. 11/307,683
→
METHOD OF FABRICATING A 3-D PACKAGE STACKING SYSTEM
App. No. 11/307,615
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT DISSIPATION ENCLOSURE
App. No. 11/354,694
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER SUPPORT
App. No. 11/307,386
→
WAFERSCALE PACKAGE SYSTEM
App. No. 11/307,363
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
App. No. 11/307,350
→
THERMALLY ENHANCED POWER SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/307,285
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/307,313
→
INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM
App. No. 11/307,315
→
MICRO CHIP-SCALE-PACKAGE SYSTEM
App. No. 11/307,314
→
STACKABLE POWER SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/307,247
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
App. No. 11/338,328
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/331,564
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PEDESTAL STRUCTURE
App. No. 11/306,808
→
STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM
App. No. 11/306,805
→
OVERHANG INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/306,693
→
METHOD OF MOUNTING AN INTEGRATED CIRCUIT PACKAGE IN AN ENCAPSULANT CAVITY
App. No. 11/306,628
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING STACKED DIE
App. No. 11/306,627
→
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM WITH DENSE ROUTABILITY AND HIGH THERMAL CONDUCTIVITY
App. No. 11/306,148
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION
App. No. 11/164,453
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATED CIRCUIT SUPPORT
App. No. 11/164,321
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING RIBBON BOND INTERCONNECT
App. No. 11/164,087
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HIGH-DENSITY SMALL FOOTPRINT SYSTEM-IN-PACKAGE
App. No. 11/163,771
→
PACKAGE STACKING LEAD FRAME SYSTEM
App. No. 11/163,770
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
App. No. 11/163,559
→
INTEGRATED CIRCUIT SOLDER BUMPING SYSTEM
App. No. 11/162,822
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/234,528
→
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
App. No. 11/160,837
→
LARGE DIE PACKAGE AND METHOD FOR THE FABRICATION THEREOF
App. No. 11/126,052
→
LEADFRAME WITH ENCAPSULANT GUIDE AND METHOD FOR THE FABRICATION THEREOF
App. No. 10/907,758
→
INTEGRATED CIRCUIT SYSTEM FOR BONDING
App. No. 10/907,732
→
MULTI-LEADFRAME SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE
App. No. 11/053,564
→
METHOD FOR SOLDER BUMPING, AND SOLDER-BUMPING STRUCTURES PRODUCED THEREBY
App. No. 11/009,436
→