IP Library Granted Patent US 7,445,962
Granted Patent B2
US 7,445,962 · App. 11/306,148 · Granted Nov 4, 2008

Stacked integrated circuits package system with dense routability and high thermal conductivity

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Quick Facts
Patent No.
US 7,445,962
App. No.
11/306,148
Granted
Nov 4, 2008
Kind
B2
Abstract

A stacked integrated circuits package system is provided providing a first substrate, mounting a first integrated circuit on a second substrate, attaching the first integrated circuit, by a side opposite the second substrate, to the first substrate, mounting a second integrated circuit to the second substrate, connecting the second integrated circuit to the first substrate, and attaching a heat spreader to the second integrated circuit and the first substrate.

Claims (44)

1. A stacked integrated circuits package system comprising:

providing a first substrate;

mounting a first integrated circuit on a second substrate;

attaching the first integrated circuit, by a side opposite the second substrate, to the first substrate;

mounting a second integrated circuit to the second substrate;

connecting the second integrated circuit to the first substrate; and

attaching a heat spreader to the second integrated circuit and the first substrate.

2. The system as claimed in claim 1 wherein attaching the first integrated circuit to the first substrate, on a side opposite the second substrate, and attaching the heat spreader to the first integrated circuit forms a heat sink for the first substrate.

3. The system as claimed in claim 1 further comprising molding an encapsulant over the first integrated circuit and the second integrated circuit.

4. The system as claimed in claim 1 wherein mounting a first integrated circuit on a second substrate comprises attaching electrical interconnects between the first integrated circuit and the second substrate.

5. The system as claimed in claim 1 wherein connecting the second integrated circuit to the first substrate comprises attaching electrical interconnects between the second integrated circuit and the first substrate.

6. A stacked integrated circuits package system comprising:

providing a first substrate;

forming first electrical interconnects on a first integrated circuit;

mounting a second substrate on the first electrical interconnects and over the first integrated circuit;

attaching the first integrated circuit, a side opposite the first electrical interconnects, on the first substrate;

stacking a second integrated circuit and a third integrated circuit on a side opposite the first electrical interconnects of the second substrate;

electrically connecting the second integrated circuit and the third integrated circuit to each other or the second substrate or the first substrate;

connecting a heat spreader to the second integrated circuit, the third integrated circuit, and the first substrate; and

molding an encapsulant over the first integrated circuit, the second integrated circuit, the third integrated circuit, the second substrate, the heat spreader, and the first substrate.

7. The system as claimed in claim 6 wherein forming the first electrical interconnects on the first integrated circuit comprises forming solder bumpers.

8. The system as claimed in claim 6 wherein attaching the first integrated circuit, the side opposite the first electrical interconnects, on the first substrate comprises attaching a first adhesive layer between the first integrated circuit and the first substrate.

9. The system as claimed in claim 6 wherein stacking a second integrated circuit and a third integrated circuit on a side opposite the first electrical interconnects of the second substrate comprises attaching a second adhesive layer between the second integrated circuit and the second substrate, and the third integrated circuit and the second substrate.

10. The system as claimed in claim 6 wherein connecting the heat spreader to the second integrated circuit, the third integrated circuit, and the first substrate comprises attaching a heat spreader adhesive from the heat spreader to the second integrated circuit, the third integrated circuit, and the first substrate.

11. A stacked integrated circuits package system comprising:

a first substrate;

a first integrated circuit on a second substrate, wherein the first integrated circuit, by a side opposite the second substrate, on the first substrate;

a second integrated circuit to the second substrate, wherein the second integrated circuit connected to the first substrate; and

a heat spreader on the second integrated circuit and the first substrate.

12. The system as claimed in claim 11 wherein the heat spreader on the second integrated circuit and the first substrate and attached to the first integrated circuit comprises a heat sink for the first substrate.

13. The system as claimed in claim 11 further comprising an encapsulant over the first integrated circuit and the second integrated circuit.

14. The system as claimed in claim 11 wherein the first integrated circuit on a second substrate comprises electrical interconnects between the first integrated circuit and the second substrate.

15. The system as claimed in claim 11 wherein the second integrated circuit to the first substrate comprises electrical interconnects between the second integrated circuit and the first substrate.

16. A stacked integrated circuits package system comprising:

a first substrate;

first electrical interconnects on a first integrated circuit;

a second substrate on the first electrical interconnects and over the first integrated circuit, wherein the first integrated circuit, a side opposite the first electrical interconnects, on the first substrate;

a second integrated circuit and a third integrated circuit on a side opposite the first electrical interconnects of the second substrate, wherein the second integrated circuit and the third integrated circuit connected to each other or the second substrate or the first substrate;

a heat spreader to the second integrated circuit, the third integrated circuit, and the first substrate; and

an encapsulant over the first integrated circuit, the second integrated circuit, the third integrated circuit, the second substrate, the heat spreader, and the first substrate.

17. The system as claimed in claim 16 wherein the first electrical interconnects on the first integrated circuit comprises forming solder bumpers.

18. The system as claimed in claim 16 wherein the first integrated circuit, the side opposite the first electrical interconnects, on the first substrate comprises a first adhesive layer between the first integrated circuit and the first substrate.

19. The system as claimed in claim 16 wherein a second integrated circuit and a third integrated circuit on a side opposite the first electrical interconnects of the second substrate comprises a second adhesive layer between the second integrated circuit and the second substrate, and the third integrated circuit and the second substrate.

20. The system as claimed in claim 16 wherein the heat spreader to the second integrated circuit, the third integrated circuit, and the first substrate comprises a heat spreader adhesive from the heat spreader to the second integrated circuit, the third integrated circuit, and the first substrate.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052938/0305 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2008
From: CHOI, BONGSUK; CHUNG, JAE HAN; KANG, KEON TEAK
To: STATS CHIPPAC LTD.
Reel/Frame 021805/0794 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2005
From: CHOI, BONGSUK; CHUNG, JAE HAN; KANG, KEON TEAK
To: STATS CHIPPAC LTD.
Reel/Frame 016907/0480 →