IP Library › Assignment 052938/0305
Patent Assignment
Reel/Frame 052938/0305

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-15 Received: 2020-06-15 Pages: 27
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (88)
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
App. No. 14/274,599
→
EMBEDDED SEMICONDUCTOR DIE PACKAGE AND METHOD OF MAKING THE SAME USING METAL FRAME CARRIER
App. No. 14/154,049
→
Semiconductor Device and Method of Making TSV Interconnect Structures Using Encapsulant for Structural Support
App. No. 14/143,891
→
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
App. No. 14/063,274
→
Semiconductor Device and Method of Forming Bump-on-Lead Interconnection
App. No. 14/021,914
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
App. No. 13/566,287
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPEN CAVITY IN TSV INTERPOSER TO CONTAIN SEMICONDUCTOR DIE IN WLCSMP
App. No. 13/420,400
→
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
App. No. 12/191,542
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 12/005,499
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ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
App. No. 11/766,095
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/690,703
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LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
App. No. 11/689,645
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
App. No. 11/671,684
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METHOD OF FABRICATING A SHIELDED STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/615,922
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INTEGRATED CIRCUIT PACKAGE WITH ELEVATED EDGE LEADFRAME
App. No. 11/610,304
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SEMICONDUCTOR PACKAGE WITH CONTROLLED SOLDER BUMP WETTING
App. No. 11/562,957
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
App. No. 11/558,413
→
WIRE SWEEP RESISTANT SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR
App. No. 11/530,802
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SPACER DIE STRUCTURE AND METHOD FOR ATTACHING
App. No. 11/464,631
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/462,537
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INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/462,320
→
LEADED STACKED PACKAGES HAVING ELEVATED DIE PADDLE
App. No. 11/459,557
→
PRE-MOLDED LEADFRAME AND METHOD THEREFOR
App. No. 11/459,317
→
MODULE HAVING STACKED CHIP SCALE SEMICONDUCTOR PACKAGES
App. No. 11/424,480
→
STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE
App. No. 11/420,873
→
OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/383,403
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INTEGRATED CIRCUIT ENCAPSULATION SYSTEM WITH VENT
App. No. 11/383,038
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OPTICAL DIE-DOWN QUAD FLAT NON-LEADED PACKAGE
App. No. 11/381,827
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWNSET LEAD
App. No. 11/381,734
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INTEGRATED CIRCUIT LEADLESS PACKAGE SYSTEM
App. No. 11/381,726
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METHOD OF FABRICATING A STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/380,596
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/379,097
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/379,106
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STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONNECTION PROTECTION
App. No. 11/278,421
→
SEMICONDUCTOR STACKED PACKAGE ASSEMBLY HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
App. No. 11/395,529
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD CLAMP LINE CRITICAL AREA HAVING WIDENED CONDUCTIVE TRACES
App. No. 11/278,343
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SEMICONDUCTOR PACKAGE INCLUDING SECOND SUBSTRATE AND HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
App. No. 11/394,635
→
SEMICONDUCTOR ASSEMBLY INCLUDING CHIP SCALE PACKAGE AND SECOND SUBSTRATE WITH EXPOSED SURFACES ON UPPER AND LOWER SIDES
App. No. 11/397,027
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/276,941
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/276,940
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MULTICHIP PACKAGE SYSTEM
App. No. 11/276,948
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INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/276,946
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DBG SYSTEM AND METHOD WITH ADHESIVE LAYER SEVERING
App. No. 11/374,377
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FLIP CHIP INTERCONNECTION PAD LAYOUT
App. No. 11/372,989
→
FLIP CHIP INTERCONNECTION PAD LAYOUT
App. No. 11/372,755
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING
App. No. 11/307,861
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STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE INTERCONNECT INTERFACE
App. No. 11/307,862
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH RECESSED SPACER
App. No. 11/307,722
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
App. No. 11/307,683
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METHOD OF FABRICATING A 3-D PACKAGE STACKING SYSTEM
App. No. 11/307,615
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT DISSIPATION ENCLOSURE
App. No. 11/354,694
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER SUPPORT
App. No. 11/307,386
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ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
App. No. 11/307,384
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
App. No. 11/307,350
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INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM
App. No. 11/307,315
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MICRO CHIP-SCALE-PACKAGE SYSTEM
App. No. 11/307,314
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
App. No. 11/338,328
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STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/331,564
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PEDESTAL STRUCTURE
App. No. 11/306,808
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STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM
App. No. 11/306,805
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OVERHANG INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/306,693
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METHOD OF MOUNTING AN INTEGRATED CIRCUIT PACKAGE IN AN ENCAPSULANT CAVITY
App. No. 11/306,628
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING STACKED DIE
App. No. 11/306,627
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STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM WITH DENSE ROUTABILITY AND HIGH THERMAL CONDUCTIVITY
App. No. 11/306,148
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATED CIRCUIT SUPPORT
App. No. 11/164,321
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STACKED DIE PACKAGE SYSTEM
App. No. 11/164,160
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING RIBBON BOND INTERCONNECT
App. No. 11/164,087
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PACKAGE STACKING LEAD FRAME SYSTEM
App. No. 11/163,770
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NESTED INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
App. No. 11/257,894
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
App. No. 11/163,559
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INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/234,528
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE RESTRAINT
App. No. 11/162,682
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/162,637
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AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE
App. No. 11/215,090
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MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
App. No. 11/160,837
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SELF-COPLANARITY BUMPING SHAPE FOR FLIP CHIP
App. No. 11/145,246
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Self-coplanarity bumping shape for flip chip
App. No. 11/145,247
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SELF-ALIGNING DOCKING SYSTEM FOR ELECTRONIC DEVICE TESTING
App. No. 10/908,433
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LARGE DIE PACKAGE AND METHOD FOR THE FABRICATION THEREOF
App. No. 11/126,052
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SEMICONDUCTOR PACKAGE WITH SELECTIVE UNDERFILL AND FABRICATION METHOD THERFOR
App. No. 11/121,847
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SEMICONDUCTOR PACKAGE WITH CONTROLLED SOLDER BUMP WETTING AND FABRICATION METHOD THEREFOR
App. No. 10/908,120
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SYSTEM FOR PEELING SEMICONDUCTOR CHIPS FROM TAPE
App. No. 10/907,991
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LEADFRAME WITH ENCAPSULANT GUIDE AND METHOD FOR THE FABRICATION THEREOF
App. No. 10/907,758
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STACKED SEMICONDUCTOR PACKAGES AND METHOD THEREFOR
App. No. 10/906,697
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AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE SYSTEM
App. No. 10/934,129
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STACKED DIE PACKAGING AND FABRICATION METHOD
App. No. 10/931,919
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MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
App. No. 10/931,654
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TORCH BUMP
App. No. 10/791,095
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