Module having stacked chip scale semiconductor packages

Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire bonding between the first and second package substrates. Also, a method for making a stacked chip scale module includes: providing a first (“top”) chip scale package including at least one first package die affixed to and electrically interconnected with a die attach side of a first package substrate, the first CSP being molded and without solder balls; dispensing adhesive on the land side of the first package substrate; providing a singulated second (“bottom”) package including at least one second package die affixed to and electrically interconnected with a die attach side of a second package substrate, the second package being molded and without solder balls; affixing the second package onto the land side of the first package substrate, a surface of the molding of the second package contacting the adhesive on the land side of the first package substrate; curing the adhesive; performing a plasma clean; forming wire bond interconnections between the land side of the second package substrate and sites in a marginal area of the land side of the first package substrate; performing a plasma clean; forming a operation to enclose the marginal areas of the land side of the first substrate, the z-interconnection wire bonds and wire loops, the edges of the second package, and the marginal area on the land side of the second package, leaving exposed an area of the land side of the second substrate located within a marginal area; attaching second level interconnect solder balls to sites on the exposed area of the second package substrate; and (where the first substrate was provided in a strip or array) saw singulating to complete a unit assembly.