IP Library Granted Patent US 7,368,319
Granted Patent B2
US 7,368,319 · App. 11/276,940 · Granted May 6, 2008

Stacked integrated circuit package-in-package system

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Quick Facts
Patent No.
US 7,368,319
App. No.
11/276,940
Granted
May 6, 2008
Kind
B2
Abstract

A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first encapsulation and a second integrated circuit package having a second encapsulation, stacking the first integrated package below the second integrated circuit package with the first encapsulation attached to the second encapsulation, forming a substrate having an opening from a substrate top surface to a substrate bottom surface, mounting the first integrated circuit package over the substrate top surface, electrically connecting the first integrated circuit package and the substrate bottom surface through the opening, and electrically connecting the second integrated circuit package and the substrate top surface.

Claims (88)

1. A stacked integrated circuit package-in-package system comprising:

forming a first integrated circuit package having a first encapsulation and a second integrated circuit package having a second encapsulation;

stacking the first integrated circuit package below the second integrated circuit package with the first encapsulation attached to the second encapsulation;

forming a substrate having an opening from a substrate top surface to a substrate bottom surface;

mounting the first integrated circuit package over the substrate top surface;

electrically connecting the first integrated circuit package and the substrate bottom surface through the opening; and

electrically connecting the second integrated circuit package and the substrate top surface.

2. The system as claimed in claim 1 wherein:

electrically connecting the first integrated circuit package and the substrate bottom surface comprises:

electrically connecting the first integrated circuit package and a contact on the substrate bottom surface; and

further comprising:

attaching an external interconnect on the contact.

3. The system as claimed in claim 1 further comprising:

mounting an integrated circuit die on the substrate top surface; and

electrically connecting the integrated circuit die and the substrate top surface.

4. The system as claimed in claim 1 further comprising:

mounting an integrated circuit die on the substrate top surface; and

electrically connecting the integrated circuit die and the substrate bottom surface through the opening.

5. The system as claimed in claim 1 further comprising:

forming a package encapsulation having a recess, the recess exposes a portion of a second package substrate of the second integrated circuit package; and

mounting a device on the second package substrate in the recess.

6. A stacked integrated circuit package-in-package system comprising:

forming a first integrated circuit package having a first encapsulation and a first substrate;

forming a second integrated circuit package having a second encapsulation and a second substrate;

stacking the first integrated circuit package below the second integrated circuit package with the first encapsulation attached to the second encapsulation with a first adhesive;

forming a package substrate having an opening from a substrate top surface to a substrate bottom surface, the substrate bottom surface has a bottom contact;

mounting the first integrated circuit package over the substrate top surface with the first substrate towards the substrate top surface;

electrically connecting the first integrated circuit package and the bottom contact of the substrate bottom surface through the opening; and

electrically connecting the second integrated circuit package and the substrate top surface.

7. The system as claimed in claim 6 further comprising electrically connecting the second substrate and the substrate top surface.

8. The system as claimed in claim 6 wherein:

electrically connecting the first integrated circuit package and the substrate bottom surface comprises:

electrically connecting the first integrated circuit package and the bottom contact on the substrate bottom surface through the opening; and

further comprising:

encapsulating the opening to form a center gate mold on the substrate bottom surface; and

attaching an external interconnect on the contact.

9. The system as claimed in claim 6 further comprising:

mounting an integrated circuit die having a central bond pad on the substrate top surface;

electrically connecting the central bond pad and the substrate bottom surface through the opening;

encapsulating the opening to form a center gate mold on the substrate bottom surface; and

attaching an external interconnect on the contact.

10. The system as claimed in claim 6 further comprising:

forming a package encapsulation having a recess, the recess exposes a portion of the second substrate; and

electrically connecting a device and a terminal pad on the second substrate in the recess.

11. A stacked integrated circuit package-in-package system comprising:

a first integrated circuit package having a first encapsulation and a second integrated circuit package having a second encapsulation;

the first integrated circuit package below the second integrated circuit package with the first encapsulation attached to the second encapsulation;

a substrate having an opening from a substrate top surface to a substrate bottom surface;

the first integrated circuit package over the substrate top surface;

a first interconnect between the first integrated circuit package and the substrate bottom surface through the opening; and

a second interconnect between the second integrated circuit package and the substrate top surface.

12. The system as claimed in claim 11 wherein:

the first interconnect between the first integrated circuit package and the substrate bottom surface comprises:

the first interconnect between the first integrated circuit package and a contact on the substrate bottom surface; and

further comprising:

an external interconnect on the contact.

13. The system as claimed in claim 11 further comprising:

an integrated circuit die on the substrate top surface; and

a second interconnect between the integrated circuit die and the substrate top surface.

14. The system as claimed in claim 11 further comprising:

an integrated circuit die on the substrate top surface; and

a second interconnect between the integrated circuit die and the substrate bottom surface through the opening.

15. The system as claimed in claim 11 further comprising:

a package encapsulation having a recess, the recess exposes a portion of a second package substrate of the second integrated circuit package; and

a device on the second package substrate in the recess.

16. The system as claimed in claim 11 wherein:

the first integrated circuit package has the first encapsulation and a first substrate;

the second integrated circuit package has the second encapsulation and a second substrate;

the first integrated circuit package is below the second integrated circuit package with the first encapsulation attached to the second encapsulation with a first adhesive;

the substrate is a package substrate with an opening from the substrate top surface to the substrate bottom surface having a bottom contact;

the first integrated circuit package is over the substrate top surface with the first substrate towards the substrate top surface;

the first interconnect is between the first integrated circuit package and the bottom contact of the substrate bottom surface through the opening; and

the second interconnect is between the second integrated circuit package and a top contact of the substrate top surface.

17. The system as claimed in claim 16 further comprising a second interconnect between the second substrate and the substrate top surface.

18. The system as claimed in claim 16 wherein:

the first interconnect between the first integrated circuit package and the substrate bottom surface comprises:

the first interconnect between the first integrated circuit package and the bottom contact on the substrate bottom surface through the opening; and

further comprising:

a package encapsulation to fill the opening and to form a center gate mold on the substrate bottom surface; and

an external interconnect on the contact.

19. The system as claimed in claim 16 further comprising:

an integrated circuit die having a central bond pad on the substrate top surface;

a second interconect between the central bond pad and the substrate bottom surface through the opening;

a package encapsulation to fill the opening and to form a center gate mold on the substrate bottom surface; and

an external interconnect on the contact.

20. The system as claimed in claim 16 further comprising:

forming a package encapsulation having a recess, the recess exposes a portion of the second substrate; and

a second interconnect between a device and a terminal pad on the second substrate in the recess.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052938/0305 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2008
From: HA, JONG-WOO; KIM, GWANG; PARK, JUHYUN
To: STATS CHIPPAC LTD.
Reel/Frame 020591/0676 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2006
From: HA, JONG-WOO; KIM, GWANG; PARK, JUHYUN
To: STATS CHIPPAC LTD.
Reel/Frame 017324/0751 →