Stacked die packaging and fabrication method
View Patent ↗A semiconductor package includes a substrate. A crenellated spacer is attached to the substrate. At least one top die is attached to the crenellated spacer. The at least one top die is wire bonded to the substrate, and an encapsulant is formed over the crenellated spacer and the at least one top die.
1. A method of manufacturing a semiconductor package comprising:
providing a substrate;
attaching a crenellated spacer to the substrate wherein the crenellated spacer comprises:
a base;
a number of merlons on the base; and
a number of embrasures intermediate adjacent ones of the number of merlons;
attaching at least one top die to at least some of the number of merlons;
wire bonding the at least one top die to the substrate; and
forming an encapsulant over the crenellated spacer and the at last one top die.
2. The method of manufacturing a semiconductor package as claimed in claim 1 further comprising:
attaching at least one of a lower die, an active component, a passive component, and combinations thereof to the substrate at least partially beneath at least one of the at least one of the top die.
3. The method of manufacturing a semiconductor package as claimed in claim 1 wherein:
attaching a crenellated spacer attaches a crenellated spacer having a formation of at least one of a closed loop, an open loop, and combinations thereof.
4. The method of manufacturing a semiconductor package as claimed in claim 1 wherein:
attaching the at least one top die to the crenellated spacer attaches the at least one top die to at least a portion of the base.
5. A method of manufacturing a semiconductor package comprising:
providing a substrate;
attaching at least one of a lower die, an active component, a passive component, and combinations thereof to the substrate;
wire bonding the at least one lower die to the substrate;
attaching a crenellated spacer to the substrate at least partially around the at least one lower die wherein the crenellated spacer comprises;
a base;
a number of merlons on the base;
a number of embrasures intermediate adjacent ones of the number of merlons;
attaching at least one top die to at least some of the number of merlons;
wire bonding the at least one top die to the substrate; and
forming an encapsulant over the at least one lower die, the crenellated spacer, and the at least one top die.
6. The method of manufacturing a semiconductor package as claimed in claim 5 wherein:
attaching a crenellated spacer attaches a crenellated spacer having a formation of at least one of a closed loop, an open loop, and combinations thereof.
7. The method of manufacturing a semiconductor package as claimed in claim 5 wherein:
attaching the at least top die to the crenellated spacer attaches the at least one top die to at least a portion of the base.
8. The method of manufacturing a semiconductor package as claimed in claim 5 wherein:
attaching a crenellated spacer attaches a ground pad.
9. A semiconductor package comprising:
a substrate;
a crenellated spacer attached to the substrate wherein the crenellated spacer comprises:
a base;
a number of merlons on the base;
a number of embrasures intermediate adjacent ones of the number of merlons;
at least one top die attached to at least some of the number of merlons;
wires bonding the at least one top die to the substrate; and
an encapsulant over the crenellated spacer and the at least one top die.
10. The semiconductor package as claimed in claim 1 further comprising:
attaching at least one of a lower die, an active component, a passive component, and combinations thereof to the substrate at least partially beneath the at least one top die.
11. The semiconductor package as claimed in claim 9 wherein:
the crenellated spacer has a formation of at least one of a closed loop, an open loop, and combinations thereof.
12. The semiconductor package as claimed in claim 9 wherein:
the at least one top die is attached to at least a portion of the base.
13. A semiconductor package comprising:
a substrate;
at least one of a lower die, an active component, a passive component, and combinations thereof attached to the substrate;
a first number of wires bonding the at least one lower die to the substrate;
a crenellated spacer attached to the substrate at least partially around the at least one lower die wherein the crenellated spacer comprises:
a base;
a number of merlons on the base;
a number of embrasures intermediate adjacent ones of the number of merlons;
at least one top die attached to at least some of the number of merlons;
a second number of wires bonding the at least one top die to the substrate; and
an encapsulant over the at least one lower die, the crenellated spacer, and the at least one top die.
14. The semiconductor package as claimed in claim 13 wherein:
the crenellated spacer has a formation of at least one of a closed loop, an open loop, and combinations thereof.
15. The method of manufacturing a semiconductor package as claimed in claim 13 wherein:
the at least one top die is attached to at least a portion of the base.
16. The method of manufacturing a semiconductor package as claimed in claim 13 wherein:
the crenellated spacer comprises a ground pad.