Patent Assignment
Reel/Frame 038378/0343
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 9
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(79)
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
App. No. 13/765,478
→
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
App. No. 13/615,308
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/464,979
→
Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
App. No. 13/423,262
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 13/367,214
→
METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
App. No. 13/355,354
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
App. No. 13/306,768
→
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
App. No. 13/237,828
→
Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads
App. No. 13/235,413
→
FLIP CHIP INTERCONNECTION STRUCTURE
App. No. 13/175,694
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 13/088,647
→
METHOD OF FABRICATING SEMICONDUCTOR DIE WITH THROUGH-HOLE VIA ON SAW STREETS AND THROUGH-HOLE VIA IN ACTIVE AREA OF DIE
App. No. 13/021,856
→
System and Method for Directional Grinding on Backside of a Semiconductor Wafer
App. No. 13/005,666
→
ULTRA THIN BUMPED WAFER WITH UNDER-FILM
App. No. 12/916,758
→
Ultra Thin Bumped Wafer With Under-Film
App. No. 12/911,592
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL GROUND PLANE AND POWER RING
App. No. 12/905,797
→
SEMICONDUCTOR WAFER HAVING THROUGH-HOLE VIAS ON SAW STREETS WITH BACKSIDE REDISTRIBUTION LAYER
App. No. 12/896,430
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
App. No. 12/858,602
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
App. No. 12/858,615
→
Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
App. No. 12/858,593
→
METHOD OF FORMING AN INDUCTOR ON A SEMICONDUCTOR WAFER
App. No. 12/826,365
→
SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
App. No. 12/813,315
→
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SAME SIZE SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIA FORMED AROUND PERIPHERY OF THE DIE
App. No. 12/788,785
→
GROOVING BUMPED WAFER PRE-UNDERFILL SYSTEM
App. No. 12/763,390
→
METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
App. No. 12/763,386
→
FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
App. No. 12/757,889
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 12/716,455
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THIN FILM CAPACITOR
App. No. 12/705,810
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPACT COILS FOR HIGH PERFORMANCE FILTER
App. No. 12/705,790
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING PASSIVE CIRCUIT ELEMENTS WITH THROUGH SILICON VIAS TO BACKSIDE INTERCONNECT STRUCTURES
App. No. 12/704,366
→
Extended Redistribution Layers Bumped Wafer
App. No. 12/704,345
→
METHOD OF FORMING QUAD FLAT PACKAGE
App. No. 12/703,450
→
SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
App. No. 12/700,114
→
SEMICONDUCTOR PACKAGE WITH PASSIVATION ISLAND FOR REDUCING STRESS ON SOLDER BUMPS
App. No. 12/651,758
→
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
App. No. 12/643,180
→
BONDING TOOL FOR MOUNTING SEMICONDUCTOR CHIPS
App. No. 12/635,536
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 12/624,482
→
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
App. No. 12/606,351
→
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
App. No. 12/579,307
→
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
App. No. 12/579,299
→
MINIATURIZED WIDE-BAND BALUNS FOR RF APPLICATIONS
App. No. 12/579,286
→
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
App. No. 12/571,234
→
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
App. No. 12/533,270
→
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
App. No. 12/533,344
→
SEMICONDUCTOR PACKAGE HAVING THROUGH-HOLE VIAS ON SAW STREETS FORMED WITH PARTIAL SAW
App. No. 12/533,160
→
THROUGH-HOLE VIA ON SAW STREETS
App. No. 12/496,046
→
WAFER LEVEL INTEGRATION PACKAGE
App. No. 12/493,108
→
INTERCONNECTING A CHIP AND A SUBSTRATE BY BONDING PURE METAL BUMPS AND PURE METAL SPOTS
App. No. 12/472,083
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 12/472,236
→
FLIP CHIP INTERCONNECTION PAD LAYOUT
App. No. 12/432,137
→
LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
App. No. 12/398,806
→
FLIP CHIP INTERCONNECT SOLDER MASK
App. No. 12/362,627
→
OPTICAL DIE-DOWN QUAD FLAT NON-LEADED PACKAGE
App. No. 12/353,489
→
CHIP SCALE PACKAGE HAVING FLIP CHIP INTERCONNECT ON DIE PADDLE
App. No. 12/191,542
→
A METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
App. No. 12/062,293
→
SPACER DIE STRUCTURE AND METHOD FOR ATTACHING
App. No. 11/464,631
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/276,941
→
DBG SYSTEM AND METHOD WITH ADHESIVE LAYER SEVERING
App. No. 11/374,377
→
FLIP CHIP INTERCONNECTION PAD LAYOUT
App. No. 11/372,989
→
FLIP CHIP INTERCONNECTION PAD LAYOUT
App. No. 11/372,755
→
ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
App. No. 11/307,384
→
STACKED DIE PACKAGE SYSTEM
App. No. 11/164,160
→
NESTED INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
App. No. 11/257,894
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE RESTRAINT
App. No. 11/162,682
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/162,637
→
AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE
App. No. 11/215,090
→
SELF-COPLANARITY BUMPING SHAPE FOR FLIP CHIP
App. No. 11/145,246
→
Self-coplanarity bumping shape for flip chip
App. No. 11/145,247
→
SELF-ALIGNING DOCKING SYSTEM FOR ELECTRONIC DEVICE TESTING
App. No. 10/908,433
→
SEMICONDUCTOR PACKAGE WITH SELECTIVE UNDERFILL AND FABRICATION METHOD THERFOR
App. No. 11/121,847
→
SEMICONDUCTOR PACKAGE WITH CONTROLLED SOLDER BUMP WETTING AND FABRICATION METHOD THEREFOR
App. No. 10/908,120
→
SYSTEM FOR PEELING SEMICONDUCTOR CHIPS FROM TAPE
App. No. 10/907,991
→
STACKED SEMICONDUCTOR PACKAGES AND METHOD THEREFOR
App. No. 10/906,697
→
AIR POCKET RESISTANT SEMICONDUCTOR PACKAGE SYSTEM
App. No. 10/934,129
→
STACKED DIE PACKAGING AND FABRICATION METHOD
App. No. 10/931,919
→
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
App. No. 10/931,654
→
FLIP CHIP INTERCONNECTION STRUCTURE
App. No. 10/850,093
→
FLIP CHIP INTERCONNECTION STRUCTURE
App. No. 10/849,947
→
TORCH BUMP
App. No. 10/791,095
→